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8 \title{Using the ECP5 for Libre-SOC prototyping
}
16 \huge{Using the ECP5 for Libre-SOC prototyping
}\\
18 \Large{Verification of the Libre-SOC core
}\\
19 \Large{using an OrangeCrab feather form factor dev board
}\\
20 \Large{and gram to drive the ddr3 ram and booting Linux
}\\
24 \large{Sponsored by NLnet
}\\
31 \frame{\frametitle{Why using an ECP5 and OrangeCrab?
}
34 \item ECP5 and ICE40 have libre toolchains (Yosys, nextpnr)
\vspace{6pt
}
35 \item Microwatt already supports the OrangeCrab using LiteDRAM: \\
36 LiteDRAM depens on original Migen and does not fit into ls2\\
37 I was unable to rebuild the original one from Microwatt\\
38 and decided to continue working on (nMigen based) gram
40 \item ECP5 is big enough for prototyping the Libre-SOC core\\
41 When I started porting ls2 to the OrangeCrab I was able to\\
42 run coldboot.c and began adding support for gram
44 \item Because for
5 years I Always Wanted To Design A GPU
46 \item ICE40 also used by Valve and Bitcraze in several SteamVR
47 products and the Lighthouse positioning deck
52 \frame{\frametitle{Why nMigen and gram?
}
57 \item nMigen+LambdaSoC port of the LiteDRAM core\\
58 avoiding using old Migen and LiteX\\
59 only using nMigen used by Libre-SOC
\vspace{10pt
}
60 \item nMigen is much more powerful than Verilog and VHDL\\
61 and easier to use for anyone that knows python\\
62 (and works with yosys/nextpnr/gcc)
\vspace{10pt
}
63 \item gram is simplified, it only supports ECP5 atm\\
64 and maybe some Xilinx FPGAs in the future
\vspace{10pt
}
65 \item Wanting to learn how to use the dram phy that comes\\
66 with the ECP5. Then booting linux using the Libre-SOC core
74 \frame{\frametitle{How do DRAM interfaces work
}
77 \item Multiple generarions of DDR-SDRAM interfaces\\
78 POWER9: DDR4-SDRAM POWER10: DDR5-SDRAM
80 \item OrangeCrab has DDR3L Memory,
128 Mbytes (
1Gbit)\\
81 64M x16,
1.35V low voltage operation (can boot linux)
83 \item See nmigen-boards for OrangeCrab pins
\vspace{3pt
}
84 \item Controller are found in gram and lite-dram
\vspace{3pt
}
85 \item Ideally gram and lite-dram should show identical behaviour\\
86 Reality: only lite-dram works out of the box
88 \item If it does not work debugging is hard\\
89 Found out that burstdet signal is not asserted on read
93 \frame{\frametitle{The ECP5 DRAM controller
}
96 \item see manual for ECP5 and ECP5-
5G High-Speed I/O Interface\\
97 comes with many built-in blocks: DQSBUFM, DDRDLLA, ...\\
98 \textit{DQSBUFM
} is the most interesting one\\
100 \item FPGA-TN-
02035-
1.3 documents DQSBUF \\
101 Data Strobe Control Block : Generates a BURSTDET output\\
102 that can be used to validate the READ pulse positioning\\
104 \item DQSBUFM element is used for all the DDR Memory\\
105 interfaces on ECP5 only. Other blocks used on Xilinx
107 \item Python implementation of DDR PHY for ECP5\\
108 git.libre-soc.org / gram.git / gram / phy / ecp5ddrphy.py\\
109 TODO same thing for microwatt / litedram\\
110 TODO http://isengaara.de/fosdem2024/ecp5ddrphy
111 %%% make url shortner
118 \frame{\frametitle{Typical DDR2/DDR3/DDR3L Memory Interface
}
120 \includegraphics[width=
0.9\textwidth]{interface1.png
}
124 \frame{\frametitle{DQSBUFM -- Inputs
}
126 \includegraphics[width=
0.9\textwidth]{DQSBUFM_P1.png
}
130 \item BURSTDET used for read leveling
131 \item DATAVALID controls dfi.phases
[0] and dfi.phases
[1] latch
135 \frame{\frametitle{DQSBUFM -- Outputs
}
137 \includegraphics[width=
0.9\textwidth]{DQSBUFM_P2.png
}
141 \item PAUSE controlled by init.pause and dqsbufm
\_manager.pause
142 \item READCLKSEL used to set read leveling delay (
3 bits)
146 \frame{\frametitle{How to use libgram
}
148 \item struct gramCtx with base addresses and user data
149 \item must call gram
\_init(ctx, profile, ddr
\_base, core
\_base, phy
\_base)
151 \item first phy is set to software control
152 \item init seq is peformed
153 \item then calibration is loaded
154 \item phy is set to hardware control back again
156 \item finally memtest must run, we can boot linux if passed
158 \item calibration is different from litedram
162 \frame{\frametitle{Read leveling in litedram
}
164 \item only read leveling used by ECP5
165 \item leveling must be done for each phy module
167 \item inner loop for bitslip
168 \item A test each read window (bitslip)
169 \item B find min/max delays
170 \item take bitslip with best score
172 \item Re-do leveling on best read window
174 \item Sync all DQSBUFM's before scan(A) / level(B)
175 \item Live demo using Microwatt
179 \frame{\frametitle{Write/readback test under software control
}
181 \item Generate pseudo-random sequence
182 \item Activate test row
183 \item Write pseudo-random sequence
185 \item ECP5: reset burstdet for current module
186 \item Read/Check pseudo-random sequence
189 \item Read back test pattern
190 \item Verify bytes matching current module
191 \item ECP5: check burstdet for current module
193 \item DQSBUFM's not synced if burstdet is
0
194 \item not yet implemented in gram
198 \frame{\frametitle{Debugging with BeagleWire
}
200 \item Fully Open iCE40 FPGA BeagleBone Cape
201 \item 32 MB SDRAM and controller written in Verilog
202 \item GPMC port access from the BeagleBone
204 \item no port to nMigen yet, toolchain on BBB
205 \item connect to ECP5 to exchange data with host PC
206 \item use SPI or I2CSlave for debugging
208 \item use as ROM emulator TODO
209 \item intercept read/write to SDRAM
210 \item run gdbserver on BeagleBoneBlack
212 \item Long term: make EOMA68 card with Solid Silicon X1
213 \item Two FPGAs and
512MB of DDR3 RAM
217 \frame{\frametitle{Porting nMigen to BeagleWire
}
219 \item There is only a LiteX port ATM
220 \item Toolchain (yosys/arachne-pnr) running on BeagleBone
221 \item Use python to control cross compile
223 \item run yosys on host PC, replace arachne-pnr
224 \item generate bitstring for multiple FPGAs if needed
225 \item control flashing via ssh, upload bitstring via scp
227 \item Unrelated to Libre-SOC: plans to make Lighthouse PMOD
228 \item LibrePlanet
2022: The LibreVR Project
229 \item http://librevr.isengaara.de
231 \item VR Headset will depend on Libre-SOC GPU
232 \item run DOOM on iCE40/ECP5 FPGA -\> VGA output needed
236 % TODO: add one more slide
238 \frame{\frametitle{Summary
}
241 \item Microwatt can boot linux+buildroot on the OrangeCrab using LiteDRAM.
242 Libre-SOC using ls2 needs more work on gram, including porting to
244 \item High speed interfaces differ between FPGA models and vendors and are hard to debug
245 without using a simulator.
246 \item Software gets more complex for larger designs, development becomes
247 more expensive. Changes easily break everything.
248 \item Once DRAM is working we can add other interfaces.
249 \item Larger FPGA may be needed to prototype advanced features including
250 GPU und display controller
251 \item We can use the BeagleWire as a host computer interface
258 {\Huge The end
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}\\
259 Thank you
\vspace{12pt
}\\
260 Questions?
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}
265 \item Discussion: http://lists.libre-soc.org
266 \item Freenode IRC \#libre-soc
267 \item http://libre-soc.org/
268 \item http://nlnet.nl/PET
269 \item https://libre-soc.org/nlnet/\#faq