interrupts/interrupt_handling.mdwn

   1 # Interrupt Handling in RISC-V
   2
   3 This is a non-authoritative document for informally capturing the
   4 requirements for interrupt handling across the spectrum of the entire
   5 RISC-V ecosystem, with a view to finding common ground.  Following on
   6 from that will be seeing where collaboration is (and is not) feasible,
   7 and, crucially, if the existing structures (such as the various PLIC
   8 implementations that already exist) cover peoples' needs (or not).
   9
  10 # Requirements Discussion
  11
  12 This section is intended for capturing requirements from different sources
  13 so that they can be viewed and compared in one place.  If you are not
  14 familiar with markdown or editing of wikis please contact
  15 luke.leighton@gmail.com, sending the appropriate text, for inclusion here.
  16
  17 * **Libre-RISCV Shakti M-Class**: a 300-400 pin SoC with almost a hundred
  18   separate and distinct "slow" (below 160mhz) peripherals that need nothing
  19   particularly special in the way of fast latency IRQs, just lots of them.
  20   Five UARTs, each requiring one IRQ line; Four I2C peripherals, each
  21   requiring two IRQ lines, Multiple Quad SPI interfaces requring **six**
  22   IRQ lines (each!), the number of IRQ lines required to cover such
  23   a significant number of peripherals begins to add up quite rapidly.
  24   However despite this, the PLIC as it stands (privspec-v-1.10 chapter 7)
  25   actually covers the requirements quite nicely, as long as it can cope
  26   with large numbers *of* IRQ lines (which it can).  Thus the Shakti
  27   PLIC Peripheral code has been modified from its original (which could
  28   handle up to XLEN separate lines) to a hierarchical arrangement that
  29   can handle up to 1024 separate and distinct IRQs
  30   <http://git.libre-riscv.org/?p=shakti-peripherals.git;a=blob;f=src/peripherals/plic/plic.bsv>
  31