simple_v_extension/specification/bitmanip.mdwn

   1 [[!tag standards]]
   2
   3 # Bitmanip opcodes
   4
   5 These are bit manipulation opcodes that, if provided, augment SimpleV for
   6 the purposes of efficiently accelerating Vector Processing, 3D Graphics
   7 and Video Processing.
   8
   9 The justification for their inclusion in BitManip is identical to the
  10 significant justification that went into their inclusion in the
  11 RISC-V Vector Extension (under the "Predicate Mask" opcodes section)
  12
  13 See
  14 <https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-mask-instructions>
  15 for details.
  16
  17 # Predicate Masks
  18
  19 SV uses standard integer scalar registers as a predicate bitmask.  Therefore,
  20 the majority of RISC-V RV32I / RV64I bit-level instructions are perfectly
  21 adequate.  Some exceptions however present themselves from RVV.
  22
  23 ## logical bit-wise instructions
  24
  25 TODO: there is an extensive table in RVV of bit-level operations:
  26
  27 output  instruction     pseudoinstruction
  28
  29 | 0 | 1 | 2 | 3 | instruction                | pseudoinstruction |
  30 | - | - | - | - | -------------------------- | ----------------- |
  31 | 0 | 0 | 0 | 0 | vmxor.mm vd, vd, vd        | vmclr.m vd        |
  32 | 1 | 0 | 0 | 0 | vmnor.mm vd, src1, src2    |                   |
  33 | 0 | 1 | 0 | 0 | vmandnot.mm vd, src2, src1 |                   |
  34 | 1 | 1 | 0 | 0 | vmnand.mm vd, src1, src1   | vmnot.m vd, src1  |
  35 | 0 | 0 | 1 | 0 | vmandnot.mm vd, src1, src2 |                   |
  36 | 1 | 0 | 1 | 0 | vmnand.mm vd, src2, src2   | vmnot.m vd, src2  |
  37 | 0 | 1 | 1 | 0 | vmxor.mm vd, src1, src2    |                   |
  38 | 1 | 1 | 1 | 0 | vmnand.mm vd, src1, src2   |                   |
  39 | 0 | 0 | 0 | 1 | vmand.mm vd, src1, src2    |                   |
  40 | 1 | 0 | 0 | 1 | vmxnor.mm vd, src1, src2   |                   |
  41 | 0 | 1 | 0 | 1 | vmand.mm vd, src2, src2    | vmcpy.m vd, src2  |
  42 | 1 | 1 | 0 | 1 | vmornot.mm vd, src2, src1  |                   |
  43 | 0 | 0 | 1 | 1 | vmand.mm vd, src1, src1    | vmcpy.m vd, src1  |
  44 | 1 | 0 | 1 | 1 | vmornot.mm vd, src1, src2  |                   |
  45 | 1 | 1 | 1 | 1 | vmxnor.mm vd, vd, vd       | vmset.m vd        |
  46
  47 ## pcnt - population count
  48
  49 population-count
  50
  51 ## ffirst - find first bit
  52
  53 finds the first bit set as an index.
  54
  55 ## sbf - set before first bit
  56
  57 Sets all LSBs leading up to where an LSB in the src is set.  If the second
  58 operand is non-zero, this process begins each time from where 1s are set in the
  59 second operand.
  60
  61      # Example
  62
  63      7 6 5 4 3 2 1 0   Bit number
  64
  65      1 0 0 1 0 1 0 0   a3 contents
  66                        sbf a2, a3, x0
  67      0 0 0 0 0 0 1 1   a2 contents
  68
  69      1 0 0 1 0 1 0 1   a3 contents
  70                        sbf a2, a3, x0
  71      0 0 0 0 0 0 0 0   a2
  72
  73      0 0 0 0 0 0 0 0   a3 contents
  74                        sbf a2, a3, x0
  75      1 1 1 1 1 1 1 1   a2
  76
  77      1 1 0 0 0 0 1 1   a0 vcontents
  78      1 0 0 1 0 1 0 0   a3 contents
  79                        sbf a2, a3, a0
  80      0 1 0 0 0 0 1 1   a2 contents
  81
  82 Pseudo-code:
  83
  84     def sbf(rd, rs1, rs2):
  85         rd = 0
  86         setting_mode = rs2 == x0 or (regs[rs2] & 1)
  87         while i < XLEN:
  88             bit = 1<<i
  89             if setting_mode:
  90                 if regs[rs1] & bit: # found a bit in rs1: stop setting rd
  91                     setting_mode = False
  92                 else:
  93                     regs[rd] |= bit
  94             else if rs2 != x0: # searching mode
  95                 if (regs[rs2] & bit):
  96                     setting_mode = True # back into "setting" mode
  97             i += 1