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[libreriscv.git] / 3d_gpu.mdwn

diff --git a/3d_gpu.mdwn b/3d_gpu.mdwn
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--- a/3d_gpu.mdwn
+++ b/3d_gpu.mdwn
@@ -1,4 +1,4 @@
-See architectural details [here](./architecture)
+See architectural details [here](./architecture), [[gaddie]] pitch and [[business_plan]]
 
 # Hybrid 3D GPU / CPU / VPU
 
@@ -11,12 +11,13 @@ are implying, a "dedicated exclusive GPU".  The option exists to *create*
 a stand-alone GPU product (contact us if this is a product that you want).
 Our primary goal is to design a **complete** all-in-one processor
 (System-on-a-Chip) that happens to include libre-licensed VPU and GPU
-accelerated instructions as part of the actual - main - CPU itself.
+accelerated instructions as part of the actual - main - CPU itself.  This greatly simplifies driver development, applications integration and debugging, reducing costs and time to market in the process.
 
 We seek investors, sponsors (whose contributions thanks to NLNet may be
 tax-deductible), engineers and potential customers, who are
 interested, as a first product, in the creation and use of an entirely
-libre low-power mobile class system-on-a-chip.  Comparative benchmark
+libre low-power mobile class system-on-a-chip
+[[shakti/m_class/]].  Comparative benchmark
 performance, pincount and price is the Allwinner A64, except that the
 power budget target is 2.5 watts in a 16x16mm 320 to 360 pin 0.8mm
 FBGA package.  Instead of single-issue higher clock rate, the design is
@@ -44,7 +45,24 @@ See [[3d_gpu/articles]] online.
 
 # Progress:
 
-* Jul 2020: first ppc64le "hello world" binary executed.  80,000 gate coriolis2 auto-layout completed with 99.95% routing. Wishbone MoU signed making available access to an additional EUR 50,000 donations from NLNet. XDC2020 and OpenPOWER conference submissions entered.
+* Dec 2021 first MMU unit tests pass, running microwatt mmu.bin.
+  Shows MMU and L1 D/I-Caches as functional in simulation.
+* Apr 2021 cocotb simulation of 180nm ASIC implemented. JTAG TAP
+  confirmed functional on ECP5 and simulation.  FreePDK-c4m45
+  created by <https://chips4makers.io>
+* Mar 2021 first SVP64 OpenPOWER augmented Cray-style instructions executed.
+  NGI POINTER EUR 200,000 grant submitted.
+* Feb 2021 FOSDEM2021, Simple-V SVP64 implementation starts in
+  simulator and Test Issuer
+* Jan 2021 FOSDEM2021 talks confirmed, NLnet crypto-primitives proposal
+  submitted, budget agreed for basic binutils and gcc SVP64 support
+* Dec 2020 work on [[openpower/sv/svp64]] started
+* Nov 2020 dry-run 180nm GDSII sent to IMEC
+* Oct 2020 [[180nm_Oct2020/ls180/]] pinouts decided, code-freeze initiated
+  for 180nm test ASIC, GDSII deadline set of Dec 2nd.
+* Sep 2020: [first boot](https://youtu.be/72QmWro9BSE) of Litex BIOS on a Versa ECP5 at 55mhz.  DDR3 RAM initialisation successful. 180nm ASIC pinouts started [[180nm_Oct2020/ls180]]
+* Aug 2020: [first boot](https://libre-soc.org/3d_gpu/libresoc_litex_bios_first_execution_2020-08-06_16-15.png) of litex BIOS in verilator simulation
+* Jul 2020: first ppc64le "hello world" binary executed.  80,000 gate coriolis2 auto-layout completed with 99.98% routing. Wishbone MoU signed making available access to an additional EUR 50,000 donations from NLNet. XDC2020 and OpenPOWER conference submissions entered.
 * Jun 2020: core unit tests and pipeline formal correctness proofs in place.
 * May 2020: first integer pipelines (ALU, Logical, Branch, Trap, SPR, ShiftRot, Mul, Div) and register files (XER, CR, INT, FAST, SPR) started.
 * Mar 2020: Coriolis2 Layout experiments successful. 6600 Memory Architecture
@@ -81,3 +99,4 @@ See [[3d_gpu/articles]] online.
 # Drivers
 
 * [[3d_gpu/opencl]]
+* [[3d_gpu/mesa]]