add WIP 256-bit add frame

[libreriscv.git] / conferences / fosdem2024 / fosdem2024_bigint / fosdem2024_bigint.tex

diff --git a/conferences/fosdem2024/fosdem2024_bigint/fosdem2024_bigint.tex b/conferences/fosdem2024/fosdem2024_bigint/fosdem2024_bigint.tex
index 8e51dbb117f0f0f68e02e1b0c2c0a066d72a2c90..832a8843014b557504a22191e8735c13abab7ae0 100644 (file)
--- a/conferences/fosdem2024/fosdem2024_bigint/fosdem2024_bigint.tex
+++ b/conferences/fosdem2024/fosdem2024_bigint/fosdem2024_bigint.tex
@@ -45,7 +45,7 @@ add r5, r17, r12
 
 \begin{frame}[fragile]
     \frametitle{Big-Integer Addition on SVP64}
-    How can we use SVP64 to add 192-bit integers?
+    How can we use SVP64 to add 256-bit integers?
     \pause
     \begin{semiverbatim}
 setvl 0, 0, 4, 0, 1, 1 # makes stuff run 4 times
@@ -61,6 +61,17 @@ adde r6, r6, r11
     \end{semiverbatim}
 \end{frame}
 
+\begin{frame}
+    \frametitle{Big-Integer Addition on an example CPU}
+    Disclaimer:
+    SVP64 is designed for everything from tiny to big and fast CPUs, this example only shows a hypothetical big and fast CPU design
+\end{frame}
+
+\begin{frame}
+    \frametitle{Big-Integer Addition on an example CPU}
+    \input{bigint-add-pipe.dia-tex}
+\end{frame}
+
 \begin{frame}
     \input{test.dia-tex}
 \end{frame}