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[libreriscv.git] / openpower / sv / rfc / ls005.mdwn

diff --git a/openpower/sv/rfc/ls005.mdwn b/openpower/sv/rfc/ls005.mdwn
index 85e101fcafb46c0cd27d72fa111612b3e64072ef..f19cf7fc5c9f9799e98135198ee9ed1e52883a35 100644 (file)
--- a/openpower/sv/rfc/ls005.mdwn
+++ b/openpower/sv/rfc/ls005.mdwn
@@ -104,9 +104,9 @@ the full width".
 * XLEN=32 overrides FPR "full width" operations to
   full BFP32, and "half width" to be "BFP16 stored in an BFP32"
 * XLEN=16 redefines FPR "full width" operations to full [IEEE BFP16](https://en.wikipedia.org/wiki/Half-precision_floating-point_format) and leaves
-  "half width" UNDEFINED (there is no IEEE version of [FP8](https://web.archive.org/web/20221223085833/https://wccftech.com/nvidia-intel-arm-bet-their-ai-future-on-fp8-whitepaper-for-8-bit-fp-published/)).
+  "half width" RESERVED (there is no IEEE version of [FP8](https://web.archive.org/web/20221223085833/https://wccftech.com/nvidia-intel-arm-bet-their-ai-future-on-fp8-whitepaper-for-8-bit-fp-published/)).
 * XLEN=8 redefines FPR "full width" operations to [bfloat16](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format) and leaves
-  "half width" UNDEFINED. 
+  "half width" RESERVED. 
 
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