# Overloadable opcodes.
-The xext proposal defines a small number N (e.g. N= 8) standardised R-type instructions xcmd0, xcmd1, ...xcmd[N-1] (preferably in the brownfield opcode space).
-Each xcmd takes (in rs1) a 12 bit "logical unit" (lun) identifying a (sub)device on the cpu that implements some "extension interface" (xintf) together with some additional data. Extension devices may be implemented in any convenient form, e.g. non standard extensions of the CPU iteself, IP tiles, or closely coupled external devices. An xintf is a set of up to N commands with 2 input and 1 output port (i.e. like an R-type instruction), together with a description of the semantics of the commands. Calling e.g. xcmd3 routes its two inputs and one output ports to command 3 on the device determined by the lun bits in rs1. Thus, the N standard xcmd instructions are standard-designated overloadable opcodes, with the non standard semantics of the opcode determined by the lun.
+The overloadable opcode (or xext) proposal allows a non standard extension to use a documented 20 + 3 bit (or 52 + 3 bit on RV64) UUID identifier for an instruction for _software_ to use. At runtime, a cpu translates the UUID to a small implementation defined 12 + 3 bit bit identifier for _hardware_ to use. It also defines a fallback mechanism for the UUID's of instructions the cpu does not recognise.
-Portable software, does not use luns directly. Instead, it goes through a level of indirection using a further instruction xext. The xext instruction translates a 20 bit globally unique identifier UUID of an xintf, to the lun of a device on the cpu that implements that xintf. The cpu can do this, because it knows (at manufacturing or boot time) which devices it has, and which xintfs they provide. This includes devices that would be described as non standard extension of the cpu if the designers had used custom opcodes instead of xintf as an interface. If the UUID of the xintf is not recognised at the current privilege level, the xext instruction returns the special lun = 0, causing any xcmd to trap. Minor variations of this scheme (requiring two more instructions xext0 and xextm1) cause xcmd instructions to fallback to always return 0 or -1 instead of trapping.
-
-Remark1: the main difference with a previous "ioctl like proposal" is that UUID translation is stateless and does not use resources. The xext instruction _neither_ initialises a device _nor_ builds global state identified by a cookie. If a device needs initialisation it can do this using xcmds as init and deinit instructions. Likewise, it can hand out cookies (which can include the lun) as a return value .
+Tl;DR see below for a C description of how this is supposed to work.
-Remark2: Implementing devices can respond to an (essentially) arbitrary number of xintfs. Hence, while an xintf is restricted to N commands, an implementing device can have an arbitrary number of commands. Organising related commands in xintfs, helps avoid UUID space pollution, and allows to amortise the (small) cost of UUID to lun translation if related commands are used in combination.
+It defines a small number N standardised R-type instructions
+xcmd0, xcmd1, ...xcmd[N-1], preferably in the brownfield opcode space. We usually assume N = 8 (aka log2(8) = 3 in the + 3 above).
+Each xcmd takes (in rs1) a 12 bit "logical unit" (lun) identifying a (sub)device on the cpu
+that implements some "extension interface" (xintf) together with some additional data.
+Extension devices may be implemented in any convenient form, e.g. non standard extensions
+of the CPU iteself, IP tiles, or closely coupled external devices.
+
+An xintf is a set of up to N commands with 2 input and 1 output port (i.e. like an
+R-type instruction), together with a description of the semantics of the commands. Calling
+e.g. xcmd3 routes its two inputs and one output ports to command 3 on the device determined
+by the lun bits in rs1. Thus, the N standard xcmd instructions are standard-designated
+overloadable opcodes, with the non standard semantics of the opcode determined by the lun.
+
+Portable software, does not use luns directly. Instead, it goes through a level of
+indirection using a further instruction xext. The xext instruction translates a 20 bit globally
+unique identifier UUID of an xintf, to the lun of a device on the cpu that implements that xintf.
+The cpu can do this, because it knows (at manufacturing or boot time) which devices it has, and
+which xintfs they provide. This includes devices that would be described as non standard extension
+of the cpu if the designers had used custom opcodes instead of xintf as an interface. If the
+UUID of the xintf is not recognised at the current privilege level, the xext instruction returns
+the special lun = 0, causing any xcmd to trap. Minor variations of this scheme (requiring two
+more instructions xext0 and xextm1) cause xcmd instructions to fallback to always return 0
+or -1 instead of trapping.
+
+Remark1: the main difference with a previous "ioctl like proposal" is that UUID translation
+is stateless and does not use resources. The xext instruction _neither_ initialises a
+device _nor_ builds global state identified by a cookie. If a device needs initialisation
+it can do this using xcmds as init and deinit instructions. Likewise, it can hand out
+cookies (which can include the lun) as a return value .
+
+Remark2: Implementing devices can respond to an (essentially) arbitrary number of xintfs.
+Hence, while an xintf is restricted to N commands, an implementing device can have an
+arbitrary number of commands. Organising related commands in xintfs, helps avoid UUID space
+pollution, and allows to amortise the (small) cost of UUID to lun translation if related
+commands are used in combination.
-Tl;DR see below for a C description of how this is supposed to work.
== Description of the instructions ==
* rs2 is arbitrary (but bit XLEN-12 to XLEN -1 is discarded)
after execution,
- rd contains the lun of a device implementing the xintf or the luns 0 (for xext), 1 (for xext0) or 2 (for xextm1).
+ if the cpu recognises the UUID and device at the current privilege level, rd contains the lun of a device
+implementing the xintf in bit 0..11, followed by bit 0.. XLEN - 13 of rs2.
+if the cpu does not recognise the UUID and device it returns the numbers 0 (for xext), 1 (for xext0) or 2 (for xextm1), in particular bit 12.. XLEN are 0.
---
The net effect is that, when the CPU implements an xintf with UUID 0xABCDE a sequence like
---
Remark:
-Quite possibly even glorified standard assembler macros are overkill and it is easier to just use defines or ordinary macro's with long names. E.g. writing
+Quite possibly even glorified standard assembler macros are overkill and it is
+easier to just use defines or ordinary macro's with long names. E.g. writing
#define org_tinker_tinker__RocknRoll__uuid 0xABCDE
#define org_tinker_tinker__RocknRoll__rock(rd, rs1, rs2) xcmd0 rd, rs1, rs2
xext rd rs1
org_tinker_tinker__RocknRoll__rock(rd, rd, rs2)
-Readability of assembler is no big deal for a compiler, but people are supposed to _document_ the semantics of the interface. In particular specifying the semantics of the xintf in same way as the semantics of the cpu should allow formal verification.
+Readability of assembler is no big deal for a compiler, but people are supposed
+to _document_ the semantics of the interface. In particular specifying the semantics
+of the xintf in same way as the semantics of the cpu should allow formal verification.
==Implications for the RiscV ecosystem ==
-
The proposal allows independent groups to define one or more extension
interfaces of (slightly crippled) R-type instructions implemented by an
extension device. Such an extension device would be an native but non standard
extension of the CPU, an IP tile or a closely coupled external chip and would
be configured at manufacturing time or bootup of the CPU.
-The 20 bit provided by the UUID of an xintf is much more room than provided by the 2 custom 32 bit, or even 4 custom 64/48 bit opcode spaces. Thus the overloadable opcodes proposal avoids most of the need to put a claim on opcode space and the associated collisions when combining independent extensions. In this respect it is similar to POSIX ioctls, which (almost) obviate the need for defining new syscalls to control new or nonstandard hardware.
+The 20 bit provided by the UUID of an xintf is much more room than provided by
+the 2 custom 32 bit, or even 4 custom 64/48 bit opcode spaces. Thus the overloadable
+opcodes proposal avoids most of the need to put a claim on opcode space,
+and the associated collisions when combining independent extensions.
+In this respect it is similar to POSIX ioctls, which (almost) obviate the need for
+defining new syscalls to control new or nonstandard hardware.
The expanded flexibility comes at the cost: the standard can specify the
semantics of the delegation mechanism and the interfacing with the rest
/*
map (UUID, device, privilege) to a 12 bit lun,
- return (lun_t){0} on unknown (at acces level)
+ return -1 on unknown (at acces level)
does associative memory lookup and tests privilege.
*/
static
- lun_t cpu__lookup_lun(const struct uuid_device_priv2lun* lun_map, uuid_dev_t uuid_dev, enum privilege priv);
+ short cpu__lookup_lun(const struct uuid_device_priv2lun* lun_map, uuid_dev_t uuid_dev, enum privilege priv, lun_t on_notfound);
+ #define org_RiscV__Trap__lun ((lun_t)0)
+ #define org_RiscV__Fallback__ReturnZero__lun ((lun_t)1)
+ #define org_RiscV__Fallback__ReturnMinusOne__lun ((lun_t)2)
lun_data_t xext(uuid_dev_t rs1, long rs2)
{
- lun_t lun = cpu__lookup_lun(lun_map, rs1, current_privilege_level());
+ short lun = cpu__lookup_lun(lun_map, rs1, current_privilege_level(), org_RiscV__Fallback__Trap__lun);
+ if(lun < 0)
+ return (lun_data_t){.lun = org_RiscV__Fallback__Trap__lun, .data = 0};
+
+ return (lun_data_t){.lun = lun, .data = rs2 % (1<< (8*sizeof(long) - 12))}
+ }
- return (lun_data_t){.lun = lun.id, .data = rs2 % (1<< (8*sizeof(long) - 12))}
+ lun_data_t xext0(uuid_dev_t rs1, long rs2)
+ {
+ short lun = cpu__lookup_lun(lun_map, rs1, current_privilege_level(), org_RiscV__Fallback__Trap__lun);
+ if(lun < 0)
+ return (lun_data_t){.lun = org_RiscV__Fallback__ReturnZero__lun, .data = 0};
+
+ return (lun_data_t){.lun = lun, .data = rs2 % (1<< (8*sizeof(long) - 12))}
+ }
+
+ lun_data_t xextm1(uuid_dev_t rs1, long rs2)
+ {
+ short lun = cpu__lookup_lun(lun_map, rs1, current_privilege_level(), org_RiscV__Fallback__Trap__lun);
+ if(lun < 0)
+ return (lun_data_t){.lun = org_RiscV__Fallback__ReturnMinusOne__lun, .data = 0};
+
+ return (lun_data_t){.lun = lun, .data = rs2 % (1<< (8*sizeof(long) - 12))}
}
template<k = 0..N-1> //pretend this is C
long xcmd<k>(lun_data_t rs1, long rs2)
{
- struct device_subdevice dev_subdev = cpu__lookup_device_subdevice(device_subdevice_map, rs1.lun, current_privilege());
+ struct device_subdevice dev_subdev = cpu__lookup_device_subdevice(device_subdevice_map, rs1.lun, current_privilege());
+
+ if(dev_subdev.devAddr == NULL)
+ cpu__trap_to(next_privilege);
+
return dev_subdev.devAddr(dev_subdev.subdevId | k >> 12 , rs1, rs2);
}
/*Fallback interfaces*/
- #define org_RiscV__Fallback__Trap__uuid 0
- #define org_RiscV__Fallback__ReturnZero__uuid 1
+ #define org_RiscV__Fallback__ReturnZero__uuid 1
#define org_RiscV__Fallback__ReturnMinusOne__uuid 2
/* fallback device */
long cpu__falback(short subdevice_xcmd, lun_data_t rs1, long rs2)
{
switch(subdevice_xcmd % (1 << 12) ){
- case 0 /* org.RiscV:Trap */: trap_to(cpu__next_higher_privilege_level());
- case 1 /* org.RiscV:ReturnZero */: return 0;
- case 2 /* org.RiscV:ReturnMinus1 */: return -1
- case 3 /* org.RiscV:Trap Machinelevel */: printf("something is rotten in machinemode: unknown xintf device"); return 31415926;
+ case 0 /* org.RiscV:ReturnZero */: return 0;
+ case 1 /* org.RiscV:ReturnMinus1 */: return -1
default: trap("hardware configuration error");
}
Example:
-
-
+ // Fake UUID's
#define com_bigbucks__Frobate__uuid 0xABCDE
#define org_tinker_tinker__RocknRoll__uuid 0x12345
- #define org_tinker_tinker__Jazz__uuid 0xD0B0D
+ #define org_tinker_tinker__Jazz__uuid 0xBEB0B
/*
com.bigbucks:Frobate{
uuid: com_bigbucks__Frobate__uuid
roll rd rs1 rs2: cmd1 rd rs1 rs2
}
+ /*
+ Device 1 implements com.bigbucks::Frobate and org.tinker.tinker interfaces, uses
+ a special command for the machine level implementation.
+ */
+
long com_bigbucks__device1(short subdevice_xcmd, lun_data_t rs1, long rs2)
{
switch(subdevice_xcmd) {
case 0 | 0 << 12 /* com.bigbucks:Frobate:frobate */ : return device1_frobate(rs1, rs2);
- case 42| 0 << 12 /* com.bigbucks:FrobateMach:frobate : return device1_frobate_machine_level(rs1, rs2);
+ case 0 | 7 << 12 /* com.bigbucks:Frobate:frobate */ : return device1_frobate_machine_level(rs1, rs2);
case 0 | 1 << 12 /* com.bigbucks:Frobate:foo */ : return device1_foo(rs1, rs2);
case 0 | 2 << 12 /* com.bigbucks:Frobate:bar */ : return device1_bar(rs1, rs2);
case 1 | 0 << 12 /* org.tinker.tinker:RocknRoll:rock */ : return device1_rock(rs1, rs2);
}
*/
+ /* Device 2 implements Frobate and Jazz interfaces */
long org_tinker_tinker__device2(short subdevice_xcmd, lun_data_t rs1, long rs2)
{
switch(dev_cmd.interfId){
}
}
+ /* cpu assigns luns to the interfaces at different privilege levels on device1 and 2 to luns at manufacturing or boot up time */
+ #define cpu__Device1__Frobate__lun ((lun_t)32)
+ #define cpu__Device1__RocknRoll__lun ((lun_t)33)
+ #define cpu__Device2__Frobate__lun ((lun_t)34)
+ #define cpu__Device2__Jazz__lun ((lun_t)35)
/* struct uuid_dev2lun_map[] */
lun_map = {
- {{.uuid_devId = {org_RiscV__Fallback__Trap__uuid , 0}, .priv = user}, .lun = 0},
- {{.uuid_devId = {org_RiscV__Fallback__Trap__uuid , 0}, .priv = super}, .lun = 0},
- {{.uuid_devId = {org_RiscV__Fallback__Trap__uuid , 0}, .priv = hyper}, .lun = 0},
- {{.uuid_devId = {org_RiscV__Fallback__Trap__uuid , 0}, .priv = mach}, .lun = 0},
- {{.uuid_devId = {org_RiscV__Fallback__ReturnZero__uuid , 0}, .priv = user}, .lun = 1},
- {{.uuid_devId = {org_RiscV__Fallback__ReturnZero__uuid , 0}, .priv = super}, .lun = 1},
- {{.uuid_devId = {org_RiscV__Fallback__ReturnZero__uuid , 0}, .priv = hyper}, .lun = 1},
- {{.uuid_devId = {org_RiscV__Fallback__ReturnZero__uuid , 0}, .priv = mach} .lun = 1},
- {{.uuid_devId = {org_RiscV__Fallback__ReturnMinusOne__uuid, 0}, .priv = user}, .lun = 2},
- {{.uuid_devId = {org_RiscV__Fallback__ReturnMinusOne__uuid, 0}, .priv = super}, .lun = 2},
- {{.uuid_devId = {org_RiscV__Fallback__ReturnMinusOne__uuid, 0}, .priv = hyper}, .lun = 2},
- {{.uuid_devId = {org_RiscV__Fallback__ReturnMinusOne__uuid, 0}, .priv = mach}, .lun = 2},
- {{.uuid_devId = {com_bigbucks__Frobate__uuid, 0}, .priv = user} .lun = 32}, //32 sic!
- {{.uuid_devId = {com_bigbucks__Frobate__uuid, 1}, .priv = super} .lun = 32},
- {{.uuid_devId = {com_bigbucks__Frobate__uuid, 1}, .priv = hyper} .lun = 32},
- {{.uuid_devId = {com_bigbucks__Frobate__uuid, 1}, .priv = mach} .lun = 32},
- {{.uuid_devId = {com_bigbucks__Frobate__uuid, 0}, .priv = super} .lun = 34}, //34 sic!
- {{.uuid_devId = {com_bigbucks__Frobate__uuid, 0}, .priv = hyper} .lun = 34},
- {{.uuid_devId = {com_bigbucks__Frobate__uuid, 0}, .priv = mach} .lun = 34},
- {{.uuid_devId = {org_tinker_tinker__RocknRoll__uuid, 0}, .priv = user} .lun = 33}, //33 sic!
- {{.uuid_devId = {org_tinker_tinker__RocknRoll__uuid, 0}, .priv = super} .lun = 33},
- {{.uuid_devId = {org_tinker_tinker__RocknRoll__uuid, 0}, .priv = hyper} .lun = 33},
- {{.uuid_devId = {org_tinker_tinker__RocknRoll__uuid, 0}, .priv = super}, .lun = 35},
- {{.uuid_devId = {org_tinker_tinker__RocknRoll__uuid, 0}, .priv = hyper}, .lun = 35},
+ {{.uuid_devId = {org_RiscV__Fallback__ReturnZero__uuid , 0}, .priv = user}, .lun = org_RiscV__Fallback__ReturnZero__lun},
+ {{.uuid_devId = {org_RiscV__Fallback__ReturnZero__uuid , 0}, .priv = super}, .lun = org_RiscV__Fallback__ReturnZero__lun},
+ {{.uuid_devId = {org_RiscV__Fallback__ReturnZero__uuid , 0}, .priv = hyper}, .lun = org_RiscV__Fallback__ReturnZero__lun},
+ {{.uuid_devId = {org_RiscV__Fallback__ReturnZero__uuid , 0}, .priv = mach} .lun = org_RiscV__Fallback__ReturnZero__lun},
+ {{.uuid_devId = {org_RiscV__Fallback__ReturnMinusOne__uuid, 0}, .priv = user}, .lun = org_RiscV__Fallback__ReturnMinusOne__lun},
+ {{.uuid_devId = {org_RiscV__Fallback__ReturnMinusOne__uuid, 0}, .priv = super}, .lun = org_RiscV__Fallback__ReturnMinusOne__lun},
+ {{.uuid_devId = {org_RiscV__Fallback__ReturnMinusOne__uuid, 0}, .priv = hyper}, .lun = org_RiscV__Fallback__ReturnMinusOne__lun},
+ {{.uuid_devId = {org_RiscV__Fallback__ReturnMinusOne__uuid, 0}, .priv = mach}, .lun = org_RiscV__Fallback__ReturnMinusOne__lun},
+ {{.uuid_devId = {com_bigbucks__Frobate__uuid, 0}, .priv = user} .lun = cpu__Device1__Frobate__lun},
+ {{.uuid_devId = {com_bigbucks__Frobate__uuid, 1}, .priv = super} .lun = cpu__Device1__Frobate__lun},
+ {{.uuid_devId = {com_bigbucks__Frobate__uuid, 1}, .priv = hyper} .lun = cpu__Device1__Frobate__lun},
+ {{.uuid_devId = {com_bigbucks__Frobate__uuid, 1}, .priv = mach} .lun = cpu__Device1__Frobate__lun},
+ {{.uuid_devId = {com_bigbucks__Frobate__uuid, 0}, .priv = super} .lun = cpu__Device2__Frobate__lun},
+ {{.uuid_devId = {com_bigbucks__Frobate__uuid, 0}, .priv = hyper} .lun = cpu__Device2__Frobate__lun},
+ {{.uuid_devId = {com_bigbucks__Frobate__uuid, 0}, .priv = mach} .lun = cpu__Device2__Frobate__lun},
+ {{.uuid_devId = {org_tinker_tinker__RocknRoll__uuid, 0}, .priv = user} .lun = cpu__Device1__RocknRoll__lun},
+ {{.uuid_devId = {org_tinker_tinker__RocknRoll__uuid, 0}, .priv = super} .lun = cpu__Device1__RocknRoll__lun},
+ {{.uuid_devId = {org_tinker_tinker__RocknRoll__uuid, 0}, .priv = hyper} .lun = cpu__Device1__RocknRoll__lun},
+ {{.uuid_devId = {org_tinker_tinker__RocknRoll__uuid, 0}, .priv = super}, .lun = cpu__Device2__Jazz__lun},
+ {{.uuid_devId = {org_tinker_tinker__RocknRoll__uuid, 0}, .priv = hyper}, .lun = cpu__Device2__Jazz__lun},
}
+ /* cpu maps luns + privilege level to busaddress of device and particular subdevice according to spec of the device.*/
/* struct lun2dev_subdevice_map[] */
dev_subdevice_map = {
- {{.lun = 0, .priv = user}, .devAddr_interfId = {fallback, 0 /* Trap */}},
- {{.lun = 0, .priv = super}, .devAddr_interfId = {fallback, 0 /* Trap */}},
- {{.lun = 0, .priv = hyper}, .devAddr_interfId = {fallback, 0 /* Trap */}},
- {{.lun = 0, .priv = mach}, .devAddr_interfId = {fallback, 3 /* Trap */}},
- {{.lun = 1, .priv = user}, .devAddr_interfId = {fallback, 1 /* ReturnZero */}},
- {{.lun = 1, .priv = super}, .devAddr_interfId = {fallback, 1 /* ReturnZero */}},
- {{.lun = 1, .priv = hyper}, .devAddr_interfId = {fallback, 1 /* ReturnZero */}},
- {{.lun = 1, .priv = mach}, .devAddr_interfId = {fallback, 1 /* ReturnZero */}},
- {{.lun = 2, .priv = user}, .devAddr_interfId = {fallback, 2 /* ReturnMinusOne*/}},
- {{.lun = 2, .priv = super}, .devAddr_interfId = {fallback, 2 /* ReturnMinusOne*/}},
- {{.lun = 2, .priv = hyper}, .devAddr_interfId = {fallback, 2 /* ReturnMinusOne*/}},
- {{.lun = 2, .priv = mach}, .devAddr_interfId = {fallback, 2 /* ReturnMinusOne*/}},
+ // .lun = 0, will trap
+ {{.lun = org_RiscV__Fallback__ReturnZero__lun, .priv = user}, .devAddr_interfId = {fallback, 1 /* ReturnZero */}},
+ {{.lun = org_RiscV__Fallback__ReturnZero__lun, .priv = super}, .devAddr_interfId = {fallback, 1 /* ReturnZero */}},
+ {{.lun = org_RiscV__Fallback__ReturnZero__lun, .priv = hyper}, .devAddr_interfId = {fallback, 1 /* ReturnZero */}},
+ {{.lun = org_RiscV__Fallback__ReturnZero__lun, .priv = mach}, .devAddr_interfId = {fallback, 1 /* ReturnZero */}},
+ {{.lun = org_RiscV__Fallback__ReturnMinusOne__lun, .priv = user}, .devAddr_interfId = {fallback, 2 /* ReturnMinusOne*/}},
+ {{.lun = org_RiscV__Fallback__ReturnMinusOne__lun, .priv = super}, .devAddr_interfId = {fallback, 2 /* ReturnMinusOne*/}},
+ {{.lun = org_RiscV__Fallback__ReturnMinusOne__lun, .priv = hyper}, .devAddr_interfId = {fallback, 2 /* ReturnMinusOne*/}},
+ {{.lun = org_RiscV__Fallback__ReturnMinusOne__lun, .priv = mach}, .devAddr_interfId = {fallback, 2 /* ReturnMinusOne*/}},
// .lun = 3 .. 7 reserved for other fallback RV interfaces
// .lun = 8 .. 30 reserved as error numbers, c.li t1 31; bltu rd t1 L_fail tests errors
- // .lun = 31 reserved out of caution
- {{.lun = 32, .priv = user}, .devAddr_interfId = {device1, 0 /* Frobate interface */}},
- {{.lun = 32, .priv = super}, .devAddr_interfId = {device1, 0 /* Frobate interface */}},
- {{.lun = 32, .priv = hyper}, .devAddr_interfId = {device1, 0 /* Frobate interface */}},
- {{.lun = 32, .priv = mach}, .devAddr_interfId = {device1,64 /* Frobate machine level interface */}},
- {{.lun = 33, .priv = user}, .devAddr_InterfId = {device1, 1 /* RocknRoll interface */}},
- {{.lun = 33, .priv = super}, .devAddr_InterfId = {device1, 1 /* RocknRoll interface */}},
- {{.lun = 33, .priv = hyper}, .devAddr_InterfId = {device1, 1 /* RocknRoll interface */}},
- {{.lun = 34, .priv = super}, .devAddr_interfId = {device2, 0 /* Frobate interface */}},
- {{.lun = 34, .priv = hyper}, .devAddr_interfId = {device2, 0 /* Frobate interface */}},
- {{.lun = 34, .priv = mach}, .devAddr_interfId = {device2, 0 /* Frobate interface */}},
- {{.lun = 35, .priv = super}, .devAddr_interfId = {device2, 1 /* Jazz interface */}},
- {{.lun = 35, .priv = hyper}, .devAddr_interfId = {device2, 1 /* Jazz interface */}},
+ // .lun = 31 reserved out of caution
+ {{.lun = cpu__Device1__Frobate__lun, .priv = user}, .devAddr_interfId = {device1, 0 /* Frobate interface */}},
+ {{.lun = cpu__Device1__Frobate__lun, .priv = super}, .devAddr_interfId = {device1, 0 /* Frobate interface */}},
+ {{.lun = cpu__Device1__Frobate__lun, .priv = hyper}, .devAddr_interfId = {device1, 0 /* Frobate interface */}},
+ {{.lun = cpu__Device1__Frobate__lun, .priv = mach}, .devAddr_interfId = {device1,64 /* Frobate machine level */}},
+ {{.lun = cpu__Device1__RocknRoll__lun, .priv = user}, .devAddr_InterfId = {device1, 1 /* RocknRoll interface */}},
+ {{.lun = cpu__Device1__RocknRoll__lun, .priv = super}, .devAddr_InterfId = {device1, 1 /* RocknRoll interface */}},
+ {{.lun = cpu__Device1__RocknRoll__lun, .priv = hyper}, .devAddr_InterfId = {device1, 1 /* RocknRoll interface */}},
+ {{.lun = cpu__Device1__RocknRoll__lun, .priv = super}, .devAddr_interfId = {device2, 1 /* Frobate interface */}},
+ {{.lun = cpu__Device2__Frobate__lun, .priv = super}, .devAddr_interfId = {device2, 0 /* Frobate interface */}},
+ {{.lun = cpu__Device2__Frobate__lun, .priv = hyper}, .devAddr_interfId = {device2, 0 /* Frobate interface */}},
+ {{.lun = cpu__Device2__Frobate__lun, .priv = mach}, .devAddr_interfId = {device2, 0 /* Frobate interface */}},
+ {{.lun = cpu__Device2__Jazz__lun, .priv = super}, .devAddr_interfId = {device2, 1 /* Jazz interface */}},
+ {{.lun = cpu__Device2__Jazz__lun, .priv = hyper}, .devAddr_interfId = {device2, 1 /* Jazz interface */}},
}
projects / libreriscv.git / blobdiff