(no commit message)

[libreriscv.git] / shakti / m_class.mdwn

diff --git a/shakti/m_class.mdwn b/shakti/m_class.mdwn
index 91870f6864fa3ea1c5dc193b3fb19723a9808ad8..3f3f7e0ec8d6d6348d979cb7b51750c9ca8d0de1 100644 (file)
--- a/shakti/m_class.mdwn
+++ b/shakti/m_class.mdwn
@@ -15,7 +15,7 @@ yields.
 ## Rough specification.
 
 Quad-core 28nm RISC-V 64-bit (RISCV64GC core with Vector SIMD Media / 3D
-extensions), 300-pin 15x15mm BGA 0.8mm pitch, 32-bit DDR3/DDR3L/LPDDR3
+extensions), 300-pin 15x15mm BGA 0.8mm pitch, 32-bit DDR3-4/LPDDR3/4
 memory interface and libre / open interfaces and accelerated hardware
 functions suitable for the higher-end, low-power, embedded, industrial
 and mobile space.
@@ -40,7 +40,7 @@ The only barrier to being able to replicate the masks from scratch
 is the proprietary cells (e.g. memory cells) designed by the Foundries:
 there is a potential long-term strategy in place to deal with that issue.
 
-The only proprietary interface utilised in the entire SoC is the DDR3
+The only proprietary interface utilised in the entire SoC is the DDR3/4
 PHY plus Controller, which will be replaced in a future revision, making
 the entire SoC exclusively designed and made from fully libre-licensed
 BSD and LGPL openly and freely accessible VLSI and VHDL source.
@@ -48,7 +48,7 @@ BSD and LGPL openly and freely accessible VLSI and VHDL source.
 In addition, no proprietary firmware whatsoever will be required to
 operate or boot the device right from the bedrock: the entire software
 stack will also be libre-licensed (even for programming the initial
-proprietary DDR3 PHY+Controller)
+proprietary DDR3/4 PHY+Controller)
 
 # Inspiration from several sources