correction

[libreriscv.git] / shakti / m_class / libre_3d_gpu.mdwn

diff --git a/shakti/m_class/libre_3d_gpu.mdwn b/shakti/m_class/libre_3d_gpu.mdwn
index 6619911639839c63c9d6e474f20ce86d8cfad541..4c001382026c5520668c0db4cf504d457e842e96 100644 (file)
--- a/shakti/m_class/libre_3d_gpu.mdwn
+++ b/shakti/m_class/libre_3d_gpu.mdwn
@@ -81,7 +81,7 @@ modifying llvm for RISC-V to do the heavy-lifting instead.
 Then it just becomes a matter of adding vector / SIMD / parallelisation
 extensions to RISC-V, and adding support in LLVM for the same:
 
->https://lists.llvm.org/pipermail/llvm-dev/2018-April/122517.html>
+<https://lists.llvm.org/pipermail/llvm-dev/2018-April/122517.html>
 
 So if considering to base the design on RISC-V, that means turning RISC-V
 into a vector processor. Now, whilst Hwacha has been located (finally),