Then it just becomes a matter of adding vector / SIMD / parallelisation
extensions to RISC-V, and adding support in LLVM for the same:
+<https://lists.llvm.org/pipermail/llvm-dev/2018-April/122517.html>
So if considering to base the design on RISC-V, that means turning RISC-V
into a vector processor. Now, whilst Hwacha has been located (finally),