add slide

[libreriscv.git] / shakti / m_class / libre_riscv_chennai_2018.tex

diff --git a/shakti/m_class/libre_riscv_chennai_2018.tex b/shakti/m_class/libre_riscv_chennai_2018.tex
index 11f3168f7d8b6f9d70b733c6315cf81bce987388..16573fde8192430bdb5c8fb6b3072ea00d79e475 100644 (file)
--- a/shakti/m_class/libre_riscv_chennai_2018.tex
+++ b/shakti/m_class/libre_riscv_chennai_2018.tex
@@ -107,7 +107,7 @@
 }
 
 
-\frame{\frametitle{So what's needed? What would a good (Libre) SoC have?}
+\frame{\frametitle{What would a good (Libre) boring, mundane SoC have?}
 
  \begin{itemize}
    \item Cover a lot of different scenarios (embedded, tablets, industrial,
@@ -196,8 +196,8 @@
 \frame{\frametitle{Proprietary vs Libre-licensed Interface HDL}
 
  \begin{itemize}
-   \item DDR3/4: challenging! \$1m for single-use, single instance\\
-         Symbiotic EDA: \$600k for PHY, CERN developed a Controller\\
+   \item DDR3/4: challenging! \$1m for single-use, single instance.\\
+         Symbiotic EDA: \$600k for PHY; CERN developed a Controller\\
          http://libre-riscv.org/shakti/m\_class/DDR/
    \item HyperRAM (JEDEC xSPI): lower risk than DDR3/4\\
           http://libre-riscv.org/shakti/m\_class/HyperRAM/