--- /dev/null
+\documentclass[slidestop]{beamer}
+\usepackage{beamerthemesplit}
+\usepackage{graphics}
+\usepackage{pstricks}
+
+\graphicspath{{./}}
+
+\title{Using the ECP5 for Libre-SOC prototyping}
+\author{Tobias Platen}
+
+
+\begin{document}
+
+\frame{
+ \begin{center}
+ \huge{Using the ECP5 for Libre-SOC prototyping}\\
+ \vspace{32pt}
+ \Large{Verification of the Libre-SOC core}\\
+ \Large{using an OrangeCrab feather form factor dev board}\\
+ \Large{and gram to drive the ddr3 ram and booting Linux}\\
+ \vspace{24pt}
+ \Large{FOSDEM2024}\\
+ \vspace{16pt}
+ \large{Sponsored by NLnet}\\
+ \vspace{6pt}
+ \large{\today}
+ \end{center}
+}
+
+
+\frame{\frametitle{Why using an ECP5 and OrangeCrab?}
+
+ \begin{itemize}
+ \item ECP5 and ICE40 have libre toolchains (Yosys, nextpnr)\vspace{6pt}
+ \item Microwatt already supports the OrangeCrab using LiteDRAM: \\
+ LiteDRAM depens on original Migen and does not fit into ls2\\
+ I was unable to rebuild the original one from Microwatt\\
+ and decided to continue working on (nMigen based) gram
+ \vspace{6pt}
+ \item ECP5 is big enough for prototyping the Libre-SOC core\\
+ When I started porting ls2 to the OrangeCrab I was able to\\
+ run coldboot.c and began adding support for gram
+ \vspace{6pt}
+ \item Because for 5 years I Always Wanted To Design A GPU
+ \vspace{6pt}
+ \item ICE40 also used by Valve and Bitcraze in several SteamVR
+ products and the Lighthouse positioning deck
+ \end{itemize}
+}
+
+
+\frame{\frametitle{Why nMigen and gram?}
+
+\vspace{15pt}
+
+ \begin{itemize}
+ \item nMigen+LambdaSoC port of the LiteDRAM core\\
+ avoiding using old Migen and LiteX\\
+ only using nMigen used by Libre-SOC\vspace{10pt}
+ \item nMigen is much more powerful than Verilog and VHDL\\
+ and easier to use for anyone that knows python\\
+ (and works with yosys/nextpnr/gcc)\vspace{10pt}
+ \item gram is simplified, it only supports ECP5 atm\\
+ and maybe some Xilinx FPGAs in the future \vspace{10pt}
+ \item Wanting to learn how to use the dram phy that comes\\
+ with the ECP5. Then booting linux using the Libre-SOC core
+ \end{itemize}
+}
+
+
+
+
+
+\frame{\frametitle{How do DRAM interfaces work}
+\vspace{9pt}
+ \begin{itemize}
+ \item Multiple generarions of DDR-SDRAM interfaces\\
+ POWER9: DDR4-SDRAM POWER10: DDR5-SDRAM
+ \vspace{3pt}
+ \item OrangeCrab has DDR3L Memory, 128 Mbytes (1Gbit)\\
+ 64M x16, 1.35V low voltage operation (can boot linux)
+ \vspace{3pt}
+ \item See nmigen-boards for OrangeCrab pins \vspace{3pt}
+ \item Controller are found in gram and lite-dram\vspace{3pt}
+ \item Ideally gram and lite-dram should show identical behaviour\\
+ Reality: only lite-dram works out of the box
+ \vspace{3pt}
+ \item If it does not work debugging is hard\\
+ Found out that burstdet signal is not asserted on read
+ \end{itemize}
+}
+
+\frame{\frametitle{The ECP5 DRAM controller}
+
+ \begin{itemize}
+ \item see manual for ECP5 and ECP5-5G High-Speed I/O Interface\\
+ comes with many built-in blocks: DQSBUFM, DDRDLLA, ...\\
+ \textit{DQSBUFM} is the most interesting one\\
+ \vspace{6pt}
+ \item FPGA-TN-02035-1.3 documents DQSBUF \\
+ Data Strobe Control Block : Generates a BURSTDET output\\
+ that can be used to validate the READ pulse positioning\\
+ \vspace{6pt}
+ \item DQSBUFM element is used for all the DDR Memory\\
+ interfaces on ECP5 only. Other blocks used on Xilinx
+ \vspace{6pt}
+ \item Python implementation of DDR PHY for ECP5\\
+ git.libre-soc.org / gram.git / gram / phy / ecp5ddrphy.py\\
+ TODO same thing for microwatt / litedram\\
+ TODO http://isengaara.de/fosdem2024/ecp5ddrphy
+ %%% make url shortner
+ \vspace{6pt}
+ \end{itemize}
+}
+
+
+
+\frame{\frametitle{Typical DDR2/DDR3/DDR3L Memory Interface}
+ \begin{center}
+ \includegraphics[width=0.9\textwidth]{interface1.png}
+ \end{center}
+}
+
+\frame{\frametitle{DQSBUFM -- Inputs}
+ \begin{center}
+ \includegraphics[width=0.9\textwidth]{DQSBUFM_P1.png}
+ \end{center}
+ \begin{itemize}
+ \vspace{3pt}
+ \item BURSTDET used for read leveling
+ \item DATAVALID controls dfi.phases[0] and dfi.phases[1] latch
+ \end{itemize}
+}
+
+\frame{\frametitle{DQSBUFM -- Outputs}
+ \begin{center}
+ \includegraphics[width=0.9\textwidth]{DQSBUFM_P2.png}
+ \end{center}
+ \begin{itemize}
+ \vspace{3pt}
+ \item PAUSE controlled by init.pause and dqsbufm\_manager.pause
+ \item READCLKSEL used to set read leveling delay (3 bits)
+ \end{itemize}
+}
+
+\frame{\frametitle{How to use libgram}
+ \begin{itemize}
+ \item struct gramCtx with base addresses and user data
+ \item must call gram\_init(ctx, profile, ddr\_base, core\_base, phy\_base)
+ \vspace{6pt}
+ \item first phy is set to software control
+ \item init seq is peformed
+ \item then calibration is loaded
+ \item phy is set to hardware control back again
+ \vspace{6pt}
+ \item finally memtest must run, we can boot linux if passed
+ \vspace{6pt}
+ \item calibration is different from litedram
+ \end{itemize}
+}
+
+\frame{\frametitle{Read leveling in litedram}
+ \begin{itemize}
+ \item only read leveling used by ECP5
+ \item leveling must be done for each phy module
+ \vspace{6pt}
+ \item inner loop for bitslip
+ \item A test each read window (bitslip)
+ \item B find min/max delays
+ \item take bitslip with best score
+ \vspace{6pt}
+ \item Re-do leveling on best read window
+ \vspace{6pt}
+ \item Sync all DQSBUFM's before scan(A) / level(B)
+ \item Live demo using Microwatt
+ \end{itemize}
+}
+
+\frame{\frametitle{Write/readback test under software control}
+ \begin{itemize}
+ \item Generate pseudo-random sequence
+ \item Activate test row
+ \item Write pseudo-random sequence
+ \vspace{6pt}
+ \item ECP5: reset burstdet for current module
+ \item Read/Check pseudo-random sequence
+ \item Precharge
+ \vspace{6pt}
+ \item Read back test pattern
+ \item Verify bytes matching current module
+ \item ECP5: check burstdet for current module
+ \vspace{9pt}
+ \item DQSBUFM's not synced if burstdet is 0
+ \item not yet implemented in gram
+ \end{itemize}
+}
+
+\frame{\frametitle{Debugging with BeagleWire}
+\begin{itemize}
+\item Fully Open iCE40 FPGA BeagleBone Cape
+\item 32 MB SDRAM and controller written in Verilog
+\item GPMC port access from the BeagleBone
+\vspace{6pt}
+\item no port to nMigen yet, toolchain on BBB
+\item connect to ECP5 to exchange data with host PC
+\item use SPI or I2CSlave for debugging
+\vspace{6pt}
+\item use as ROM emulator TODO
+\item intercept read/write to SDRAM
+\item run gdbserver on BeagleBoneBlack
+\vspace{9pt}
+\item Long term: make EOMA68 card with Solid Silicon X1
+\item Two FPGAs and 512MB of DDR3 RAM
+\end{itemize}
+}
+
+\frame{\frametitle{Porting nMigen to BeagleWire}
+\begin{itemize}
+\item There is only a LiteX port ATM
+\item Toolchain (yosys/arachne-pnr) running on BeagleBone
+\item Use python to control cross compile
+\vspace{6pt}
+\item run yosys on host PC, replace arachne-pnr
+\item generate bitstring for multiple FPGAs if needed
+\item control flashing via ssh, upload bitstring via scp
+\vspace{6pt}
+\item Unrelated to Libre-SOC: plans to make Lighthouse PMOD
+\item LibrePlanet 2022: The LibreVR Project
+\item http://librevr.isengaara.de
+\vspace{9pt}
+\item VR Headset will depend on Libre-SOC GPU
+\item run DOOM on iCE40/ECP5 FPGA -\> VGA output needed
+\end{itemize}
+}
+
+% TODO: add one more slide
+
+\frame{\frametitle{Summary}
+
+ \begin{itemize}
+ \item Microwatt can boot linux+buildroot on the OrangeCrab using LiteDRAM.
+ Libre-SOC using ls2 needs more work on gram, including porting to
+ other FPGAs.
+ \item High speed interfaces differ between FPGA models and vendors and are hard to debug
+ without using a simulator.
+ \item Software gets more complex for larger designs, development becomes
+ more expensive. Changes easily break everything.
+ \item Once DRAM is working we can add other interfaces.
+ \item Larger FPGA may be needed to prototype advanced features including
+ GPU und display controller
+ \item We can use the BeagleWire as a host computer interface
+ \end{itemize}
+}
+
+
+\frame{
+ \begin{center}
+ {\Huge The end\vspace{12pt}\\
+ Thank you\vspace{12pt}\\
+ Questions?\vspace{12pt}
+}
+ \end{center}
+
+ \begin{itemize}
+ \item Discussion: http://lists.libre-soc.org
+ \item Freenode IRC \#libre-soc
+ \item http://libre-soc.org/
+ \item http://nlnet.nl/PET
+ \item https://libre-soc.org/nlnet/\#faq
+ \end{itemize}
+}
+
+
+\end{document}
projects / libreriscv.git / commitdiff
