add B extension proposal
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 2 Apr 2018 12:26:59 +0000 (13:26 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 2 Apr 2018 12:26:59 +0000 (13:26 +0100)
shakti/m_class.mdwn

index 71fea274dfaa2e27bd1980ab2133489bfde97004..ed3953b49c11077a3e3ee3a5ec2d65e0b6b2506e 100644 (file)
@@ -352,6 +352,6 @@ many more.
 * <http://n64devkit.square7.ch/qa/graphics/ucode.htm>
 * <https://dac.com/media-center/exhibitor-news/synopsys%E2%80%99-designware-universal-ddr-memory-controller-delivers-30-percent> 110nm DDR3 PHY
 * <https://bitbucket.org/cfelton/minnesota> myhdl HDL cores
-
+* B Extension proposal <https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/zi_7B15kj6s>
 [[!tag cpus]]