(no commit message)

diff --git a/openpower/sv/po9_encoding.mdwn b/openpower/sv/po9_encoding.mdwn
index 310c20cb4a2ba0eb2b9e379f238f412b7e9f0fd9..5e186dfcb1fd3ef25e64300626feda1c2f3832fc 100644 (file)
--- a/openpower/sv/po9_encoding.mdwn
+++ b/openpower/sv/po9_encoding.mdwn
@@ -7,9 +7,20 @@
 In its simpest form, SVP64 is a 32-bit Prefix conceptually similar to Intel 8086 `REP`
 instruction that both augments its following Defined Word Suffix, and also may
 repeat that instruction with optional sequential register offsets from those given in the 
-Suffix. More advanced features add predication, element-width overrides, and Vertical-First
+Suffix. Register numbers may also be extended (larger register files).
+More advanced features add predication, element-width overrides, and Vertical-First
 Mode.
 
+**Definition of Vertical-First:**
+
+Normal Cray-style Vectorisation, designated Horizontal-First, performs element-level
+operations (often in parallel) before moving in the usual fashion to the next
+instruction. Vertical-First on the other hand executes *one element operation only*
+then moves on to the next instruction, whereupon if that is also an SVP64-Prefixed
+instruction the exact same element offset is used.  Element offsets are then explicitly
+advanced by calling a special instruction, `svstep`. The term "Vertical-First"
+stems from visually listing program instructions vertically and register files horizontally.
+
 **Definition of SVP64Single Prefixing:**
 
 A 32-bit Prefix in front of a Defined Word that extends register numbers