rename fmv[ft]g*/fcvt[ft]g* to m[tf]fpr*/c[tf]fpr*

diff --git a/openpower/power_trans_ops.mdwn b/openpower/power_trans_ops.mdwn
index 99b4b98de8769cd26c584dfcfbee97f09e9b87cb..e6f1dcb33a66fa546333e89267f177bd1c4c05b9 100644 (file)
--- a/openpower/power_trans_ops.mdwn
+++ b/openpower/power_trans_ops.mdwn
@@ -24,11 +24,11 @@ Parenthesized entries are not part of fptrans.
 
 | XO LSB half &#x2192;<br> XO MSB half &#x2193; | 01100                                              | 01101                                              | 01110                                                   | 01111                                                   |
 |-----------------------------------------------|----------------------------------------------------|----------------------------------------------------|---------------------------------------------------------|---------------------------------------------------------|
-| 11000                                         | <small>`11000 01100`</small><br>fexp2m1(s) (draft) | <small>`11000 01101`</small><br>flog2p1(s) (draft) | <small>`11000 01110`</small><br>(fcvttgo) (draft)       | <small>`11000 01111`</small><br>(fcvtfg(s)) (draft)     |
+| 11000                                         | <small>`11000 01100`</small><br>fexp2m1(s) (draft) | <small>`11000 01101`</small><br>flog2p1(s) (draft) | <small>`11000 01110`</small><br>(cffpro) (draft)       | <small>`11000 01111`</small><br>(ctfpr(s)) (draft)     |
 | 11001                                         | <small>`11001 01100`</small><br>fexpm1(s) (draft)  | <small>`11001 01101`</small><br>flogp1(s) (draft)  | <small>`11001 01110`</small><br>(fctid)                 | <small>`11001 01111`</small><br>(fctidz)                |
 | 11010                                         | <small>`11010 01100`</small><br>fexp10m1(s) (draft)| <small>`11010 01101`</small><br>flog10p1(s) (draft)| <small>`11010 01110`</small><br>(fcfid(s))              | <small>`11010 01111`</small><br>fmod(s) (draft)         |
 | 11011                                         | <small>`11011 01100`</small><br>fpown(s) (draft)   | <small>`11011 01101`</small><br>frootn(s) (draft)  | <small>`11011 01110`</small><br>&nbsp;                  | <small>`11011 01111`</small><br>&nbsp;                  |
-| 11100                                         | <small>`11100 01100`</small><br>fexp2(s) (draft)   | <small>`11100 01101`</small><br>flog2(s) (draft)   | <small>`11100 01110`</small><br>(fmvtg(s)) (draft)      | <small>`11100 01111`</small><br>(fmvfg(s)) (draft)      |
+| 11100                                         | <small>`11100 01100`</small><br>fexp2(s) (draft)   | <small>`11100 01101`</small><br>flog2(s) (draft)   | <small>`11100 01110`</small><br>(mffpr(s)) (draft)      | <small>`11100 01111`</small><br>(mtfpr(s)) (draft)      |
 | 11101                                         | <small>`11101 01100`</small><br>fexp(s) (draft)    | <small>`11101 01101`</small><br>flog(s) (draft)    | <small>`11101 01110`</small><br>(fctidu)                | <small>`11101 01111`</small><br>(fctiduz)               |
 | 11110                                         | <small>`11110 01100`</small><br>fexp10(s) (draft)  | <small>`11110 01101`</small><br>flog10(s) (draft)  | <small>`11110 01110`</small><br>(fcfidu(s))             | <small>`11110 01111`</small><br>fremainder(s) (draft)   |
 | 11111                                         | <small>`11111 01100`</small><br>fpowr(s) (draft)   | <small>`11111 01101`</small><br>fpow(s) (draft)    | <small>`11111 01110`</small><br>&nbsp;                  | <small>`11111 01111`</small><br>&nbsp;                  |

diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn
index 6da7b0e971ba853fe7e58b2ab01de75fae80337d..f934f33405d657276fff4d3145e7ddaeebc567ab 100644 (file)
--- a/openpower/sv/int_fp_mv.mdwn
+++ b/openpower/sv/int_fp_mv.mdwn
@@ -116,7 +116,7 @@ are explained in the  [[int_fp_mv/appendix]]
 
 # Float load immediate  <a name="fmvis"></a>
 
-These are like a variant of `fmvfg` and `oris`, combined.
+These are like a variant of `mtfpr` and `oris`, combined.
 Power ISA currently requires a large
 number of instructions to get Floating Point constants into registers.
 `fmvis` on its own is equivalent to BF16 to FP32/64 conversion,

diff --git a/openpower/sv/int_fp_mv/appendix.mdwn b/openpower/sv/int_fp_mv/appendix.mdwn
index b94fadaa2d0025a318774c3a8f018b3aa4973092..55fb19abe68fdb195a5b90c163209045aebd35f0 100644 (file)
--- a/openpower/sv/int_fp_mv/appendix.mdwn
+++ b/openpower/sv/int_fp_mv/appendix.mdwn
@@ -24,10 +24,10 @@ over-ridden.  Simple-V therefore sets the following
 
 Examples:
 
-* `sv.fmvtg/sw=32 RT.v, FRA.v` is defined as treating FRA
+* `sv.mffpr/sw=32 RT.v, FRA.v` is defined as treating FRA
    as a vector of *FP32* source operands each *32* bits wide
    which are to be placed into *64* bit integer destination elements.
-* `sv.fmvfgs/dw=32 FRT.v, RA.v` is defined as taking the bottom
+* `sv.mtfprs/dw=32 FRT.v, RA.v` is defined as taking the bottom
    32 bits of each RA integer source, then performing a **32 bit**
    FP32 to **FP16** conversion and storing the result in the
    **32 bits** of an FRT destination element.
@@ -100,19 +100,19 @@ toInt32(double):
 ## Rust
 
 ```
-pub fn fcvttgd_rust(v: f64) -> i64 {
+pub fn cffprd_rust(v: f64) -> i64 {
     v as i64
 }
 
-pub fn fcvttgud_rust(v: f64) -> u64 {
+pub fn cffprud_rust(v: f64) -> u64 {
     v as u64
 }
 
-pub fn fcvttgw_rust(v: f64) -> i32 {
+pub fn cffprw_rust(v: f64) -> i32 {
     v as i32
 }
 
-pub fn fcvttguw_rust(v: f64) -> u32 {
+pub fn cffpruw_rust(v: f64) -> u32 {
     v as u32
 }
 ```
@@ -124,7 +124,7 @@ pub fn fcvttguw_rust(v: f64) -> u32 {
         .long   0xdf000000
 .LCPI0_1:
         .quad   0x43dfffffffffffff
-example::fcvttgd_rust:
+example::cffprd_rust:
 .Lfunc_gep0:
         addis 2, 12, .TOC.-.Lfunc_gep0@ha
         addi 2, 2, .TOC.-.Lfunc_gep0@l
@@ -158,7 +158,7 @@ example::fcvttgd_rust:
         .long   0x00000000
 .LCPI1_1:
         .quad   0x43efffffffffffff
-example::fcvttgud_rust:
+example::cffprud_rust:
 .Lfunc_gep1:
         addis 2, 12, .TOC.-.Lfunc_gep1@ha
         addi 2, 2, .TOC.-.Lfunc_gep1@l
@@ -187,7 +187,7 @@ example::fcvttgud_rust:
         .long   0xcf000000
 .LCPI2_1:
         .quad   0x41dfffffffc00000
-example::fcvttgw_rust:
+example::cffprw_rust:
 .Lfunc_gep2:
         addis 2, 12, .TOC.-.Lfunc_gep2@ha
         addi 2, 2, .TOC.-.Lfunc_gep2@l
@@ -221,7 +221,7 @@ example::fcvttgw_rust:
         .long   0x00000000
 .LCPI3_1:
         .quad   0x41efffffffe00000
-example::fcvttguw_rust:
+example::cffpruw_rust:
 .Lfunc_gep3:
         addis 2, 12, .TOC.-.Lfunc_gep3@ha
         addi 2, 2, .TOC.-.Lfunc_gep3@l

diff --git a/openpower/sv/int_fp_mv/moves_and_conversions.mdwn b/openpower/sv/int_fp_mv/moves_and_conversions.mdwn
index 550f9e8902192aac6c8a2c3b739ca2dfc9f0e1c7..7a36c7f9b277f97aab117216943f77eeda34a916 100644 (file)
--- a/openpower/sv/int_fp_mv/moves_and_conversions.mdwn
+++ b/openpower/sv/int_fp_mv/moves_and_conversions.mdwn
@@ -2,7 +2,7 @@
 # Immediate Tables
 
 Tables that are used by
-`fmvtg[s][.]`/`fmvfg[s]`/`fcvttg[o][.]`/`fcvtfg[s][.]`:
+`mffpr[s][.]`/`mtfpr[s]`/`cffpr[o][.]`/`ctfpr[s][.]`:
 
 ## `IT` -- Integer Type
 
@@ -39,8 +39,8 @@ File to another.
 ## Floating Move To GPR
 
 ```
-    fmvtg RT, FRB
-    fmvtg. RT, FRB
+    mffpr RT, FRB
+    mffpr. RT, FRB
 ```
 
 | 0-5 | 6-10 | 11-15 | 16-20 | 21-30 | 31 | Form   |
@@ -53,7 +53,7 @@ File to another.
 
 Move a 64-bit float from a FPR to a GPR, just copying bits of the IEEE 754
 representation directly. This is equivalent to `stfd` followed by `ld`.
-As `fmvtg` is just copying bits, `FPSCR` is not affected in any way. `fmvtg` is
+As `mffpr` is just copying bits, `FPSCR` is not affected in any way. `mffpr` is
 similar to `mfvsrd`, except doesn't require VSX, which is useful for SFFS
 implementations.
 
@@ -71,8 +71,8 @@ Special Registers altered:
 ## Floating Move To GPR Single
 
 ```
-    fmvtgs RT, FRB
-    fmvtgs. RT, FRB
+    mffprs RT, FRB
+    mffprs. RT, FRB
 ```
 
 | 0-5 | 6-10 | 11-15 | 16-20 | 21-30 | 31 | Form   |
@@ -86,7 +86,7 @@ Special Registers altered:
 Move a BFP32 from a FPR to a GPR, by using `SINGLE` to extract the standard
 `BFP32` form from FRB and zero-extending the result to 64-bits and storing to
 RT. This is equivalent to `stfs` followed by `lwz`.
-As `fmvtgs` is just copying the BFP32 form, `FPSCR` is not affected in any way.
+As `mffprs` is just copying the BFP32 form, `FPSCR` is not affected in any way.
 
 Rc=1 tests RT and sets CR0, exactly like all other Scalar Fixed-Point
 operations.
@@ -104,7 +104,7 @@ Special Registers altered:
 ## Double-Precision Floating Move From GPR
 
 ```
-    fmvfg FRT, RB
+    mtfpr FRT, RB
 ```
 
 | 0-5 | 6-10 | 11-15 | 16-20 | 21-30 | 31 | Form   |
@@ -117,7 +117,7 @@ Special Registers altered:
 
 move a 64-bit float from a GPR to a FPR, just copying bits of the IEEE 754
 representation directly. This is equivalent to `std` followed by `lfd`.
-As `fmvfg` is just copying bits, `FPSCR` is not affected in any way. `fmvfg` is
+As `mtfpr` is just copying bits, `FPSCR` is not affected in any way. `mtfpr` is
 similar to `mtvsrd`, except doesn't require VSX, which is useful for SFFS
 implementations.
 
@@ -132,7 +132,7 @@ Special Registers altered:
 ## Floating Move From GPR Single
 
 ```
-    fmvfgs FRT, RB
+    mtfprs FRT, RB
 ```
 
 | 0-5 | 6-10 | 11-15 | 16-20 | 21-30 | 31 | Form   |
@@ -146,7 +146,7 @@ Special Registers altered:
 Move a BFP32 from a GPR to a FPR, by using `DOUBLE` on the least significant
 32-bits of RB to do the standard BFP32 in BFP64 trick and store the result in
 FRT. This is equivalent to `stw` followed by `lfs`.
-As `fmvfgs` is just copying the BFP32 form, `FPSCR` is not affected in any way.
+As `mtfprs` is just copying the BFP32 form, `FPSCR` is not affected in any way.
 
 Special Registers altered:
 
@@ -168,8 +168,8 @@ as exceptions.
 ## Double-Precision Floating Convert From Integer In GPR
 
 ```
-    fcvtfg FRT, RB, IT
-    fcvtfg. FRT, RB, IT
+    ctfpr FRT, RB, IT
+    ctfpr. FRT, RB, IT
 ```
 
 | 0-5 | 6-10 | 11-12 | 13-15 | 16-20 | 21-30 | 31 | Form   |
@@ -233,14 +233,14 @@ Special Registers altered:
 
 | Assembly Alias       | Full Instruction     |
 |----------------------|----------------------|
-| `fcvtfgw FRT, RB`    | `fcvtfg FRT, RB, 0`  |
-| `fcvtfgw. FRT, RB`   | `fcvtfg. FRT, RB, 0` |
-| `fcvtfguw FRT, RB`   | `fcvtfg FRT, RB, 1`  |
-| `fcvtfguw. FRT, RB`  | `fcvtfg. FRT, RB, 1` |
-| `fcvtfgd FRT, RB`    | `fcvtfg FRT, RB, 2`  |
-| `fcvtfgd. FRT, RB`   | `fcvtfg. FRT, RB, 2` |
-| `fcvtfgud FRT, RB`   | `fcvtfg FRT, RB, 3`  |
-| `fcvtfgud. FRT, RB`  | `fcvtfg. FRT, RB, 3` |
+| `ctfprw FRT, RB`    | `ctfpr FRT, RB, 0`  |
+| `ctfprw. FRT, RB`   | `ctfpr. FRT, RB, 0` |
+| `ctfpruw FRT, RB`   | `ctfpr FRT, RB, 1`  |
+| `ctfpruw. FRT, RB`  | `ctfpr. FRT, RB, 1` |
+| `ctfprd FRT, RB`    | `ctfpr FRT, RB, 2`  |
+| `ctfprd. FRT, RB`   | `ctfpr. FRT, RB, 2` |
+| `ctfprud FRT, RB`   | `ctfpr FRT, RB, 3`  |
+| `ctfprud. FRT, RB`  | `ctfpr. FRT, RB, 3` |
 
 ----------
 
@@ -249,8 +249,8 @@ Special Registers altered:
 ## Floating Convert From Integer In GPR Single
 
 ```
-    fcvtfgs FRT, RB, IT
-    fcvtfgs. FRT, RB, IT
+    ctfprs FRT, RB, IT
+    ctfprs. FRT, RB, IT
 ```
 
 | 0-5 | 6-10 | 11-12 | 13-15 | 16-20 | 21-30 | 31 | Form   |
@@ -302,14 +302,14 @@ Special Registers altered:
 
 | Assembly Alias       | Full Instruction     |
 |----------------------|----------------------|
-| `fcvtfgws FRT, RB`   | `fcvtfg FRT, RB, 0`  |
-| `fcvtfgws. FRT, RB`  | `fcvtfg. FRT, RB, 0` |
-| `fcvtfguws FRT, RB`  | `fcvtfg FRT, RB, 1`  |
-| `fcvtfguws. FRT, RB` | `fcvtfg. FRT, RB, 1` |
-| `fcvtfgds FRT, RB`   | `fcvtfg FRT, RB, 2`  |
-| `fcvtfgds. FRT, RB`  | `fcvtfg. FRT, RB, 2` |
-| `fcvtfguds FRT, RB`  | `fcvtfg FRT, RB, 3`  |
-| `fcvtfguds. FRT, RB` | `fcvtfg. FRT, RB, 3` |
+| `ctfprws FRT, RB`   | `ctfpr FRT, RB, 0`  |
+| `ctfprws. FRT, RB`  | `ctfpr. FRT, RB, 0` |
+| `ctfpruws FRT, RB`  | `ctfpr FRT, RB, 1`  |
+| `ctfpruws. FRT, RB` | `ctfpr. FRT, RB, 1` |
+| `ctfprds FRT, RB`   | `ctfpr FRT, RB, 2`  |
+| `ctfprds. FRT, RB`  | `ctfpr. FRT, RB, 2` |
+| `ctfpruds FRT, RB`  | `ctfpr FRT, RB, 3`  |
+| `ctfpruds. FRT, RB` | `ctfpr. FRT, RB, 3` |
 
 ----------
 
@@ -457,10 +457,10 @@ Section 7.1 of the ECMAScript / JavaScript
 ## Double-Precision Floating Convert To Integer In GPR
 
 ```
-    fcvttg RT, FRB, CVM, IT
-    fcvttg. RT, FRB, CVM, IT
-    fcvttgo RT, FRB, CVM, IT
-    fcvttgo. RT, FRB, CVM, IT
+    cffpr RT, FRB, CVM, IT
+    cffpr. RT, FRB, CVM, IT
+    cffpro RT, FRB, CVM, IT
+    cffpro. RT, FRB, CVM, IT
 ```
 
 | 0-5 | 6-10 | 11-12 | 13-15 | 16-20 | 21 | 22-30 | 31 | Form    |
@@ -601,19 +601,19 @@ Special Registers altered:
 
 | Assembly Alias            | Full Instruction           |
 |---------------------------|----------------------------|
-| `fcvttgw RT, FRB, CVM`    | `fcvttg RT, FRB, CVM, 0`   |
-| `fcvttgw. RT, FRB, CVM`   | `fcvttg. RT, FRB, CVM, 0`  |
-| `fcvttgwo RT, FRB, CVM`   | `fcvttgo RT, FRB, CVM, 0`  |
-| `fcvttgwo. RT, FRB, CVM`  | `fcvttgo. RT, FRB, CVM, 0` |
-| `fcvttguw RT, FRB, CVM`   | `fcvttg RT, FRB, CVM, 1`   |
-| `fcvttguw. RT, FRB, CVM`  | `fcvttg. RT, FRB, CVM, 1`  |
-| `fcvttguwo RT, FRB, CVM`  | `fcvttgo RT, FRB, CVM, 1`  |
-| `fcvttguwo. RT, FRB, CVM` | `fcvttgo. RT, FRB, CVM, 1` |
-| `fcvttgd RT, FRB, CVM`    | `fcvttg RT, FRB, CVM, 2`   |
-| `fcvttgd. RT, FRB, CVM`   | `fcvttg. RT, FRB, CVM, 2`  |
-| `fcvttgdo RT, FRB, CVM`   | `fcvttgo RT, FRB, CVM, 2`  |
-| `fcvttgdo. RT, FRB, CVM`  | `fcvttgo. RT, FRB, CVM, 2` |
-| `fcvttgud RT, FRB, CVM`   | `fcvttg RT, FRB, CVM, 3`   |
-| `fcvttgud. RT, FRB, CVM`  | `fcvttg. RT, FRB, CVM, 3`  |
-| `fcvttgudo RT, FRB, CVM`  | `fcvttgo RT, FRB, CVM, 3`  |
-| `fcvttgudo. RT, FRB, CVM` | `fcvttgo. RT, FRB, CVM, 3` |
+| `cffprw RT, FRB, CVM`    | `cffpr RT, FRB, CVM, 0`   |
+| `cffprw. RT, FRB, CVM`   | `cffpr. RT, FRB, CVM, 0`  |
+| `cffprwo RT, FRB, CVM`   | `cffpro RT, FRB, CVM, 0`  |
+| `cffprwo. RT, FRB, CVM`  | `cffpro. RT, FRB, CVM, 0` |
+| `cffpruw RT, FRB, CVM`   | `cffpr RT, FRB, CVM, 1`   |
+| `cffpruw. RT, FRB, CVM`  | `cffpr. RT, FRB, CVM, 1`  |
+| `cffpruwo RT, FRB, CVM`  | `cffpro RT, FRB, CVM, 1`  |
+| `cffpruwo. RT, FRB, CVM` | `cffpro. RT, FRB, CVM, 1` |
+| `cffprd RT, FRB, CVM`    | `cffpr RT, FRB, CVM, 2`   |
+| `cffprd. RT, FRB, CVM`   | `cffpr. RT, FRB, CVM, 2`  |
+| `cffprdo RT, FRB, CVM`   | `cffpro RT, FRB, CVM, 2`  |
+| `cffprdo. RT, FRB, CVM`  | `cffpro. RT, FRB, CVM, 2` |
+| `cffprud RT, FRB, CVM`   | `cffpr RT, FRB, CVM, 3`   |
+| `cffprud. RT, FRB, CVM`  | `cffpr. RT, FRB, CVM, 3`  |
+| `cffprudo RT, FRB, CVM`  | `cffpro RT, FRB, CVM, 3`  |
+| `cffprudo. RT, FRB, CVM` | `cffpro. RT, FRB, CVM, 3` |

diff --git a/openpower/sv/rfc/ls006.fpintmv.mdwn b/openpower/sv/rfc/ls006.fpintmv.mdwn
index 7a9cf8822329754dc6c591176e9444bcf87cf77f..e0cef90222f0488ed82a73a387182a3088cfc905 100644 (file)
--- a/openpower/sv/rfc/ls006.fpintmv.mdwn
+++ b/openpower/sv/rfc/ls006.fpintmv.mdwn
@@ -30,16 +30,16 @@
 
 Single-precision Instructions added:
 
-* `fmvtgs` -- Single-Precision Floating Move To GPR
-* `fmvfgs` -- Single-Precision Floating Move From GPR
-* `fcvtfgs` -- Single-Precision Floating Convert From Integer In GPR
+* `mffprs` -- Single-Precision Floating Move To GPR
+* `mtfprs` -- Single-Precision Floating Move From GPR
+* `ctfprs` -- Single-Precision Floating Convert From Integer In GPR
 
 Identical (except Double-precision) Instructions added:
 
-* `fmvtg` -- Double-Precision Floating Move To GPR
-* `fmvfg` -- Double-Precision Floating Move From GPR
-* `fcvttg` -- Double-Precision Floating Convert To Integer In GPR
-* `fcvtfg` -- Double-Precision Floating Convert From Integer In GPR
+* `mffpr` -- Double-Precision Floating Move To GPR
+* `mtfpr` -- Double-Precision Floating Move From GPR
+* `cffpr` -- Double-Precision Floating Convert To Integer In GPR
+* `ctfpr` -- Double-Precision Floating Convert From Integer In GPR
 
 **Submitter**: Luke Leighton (Libre-SOC)
 

diff --git a/openpower/sv/rfc/ls012/optable.csv b/openpower/sv/rfc/ls012/optable.csv
index 96885cf50fbde9e3fe3d7d9b3bf14373392fbc04..5a7a9005aee14e144b55473a2c3134d6b006469d 100644 (file)
--- a/openpower/sv/rfc/ls012/optable.csv
+++ b/openpower/sv/rfc/ls012/optable.csv
@@ -126,10 +126,10 @@ mcrfm,     ls015, high, 9, yes, EXT0xx, no, sv/cr_int_predication, 2r1w, SFFS, T
 # fclass (Scalar variant of xvtstdcsp)
 fptstp(s),   TBD,   high,  10, yes, EXT0xx, no, sv/fclass, 1R1w, SFFS, TODO
 # INT<->FP mv, TBD
-fmvtg(s),    ls006.fpintmv, high, 10, yes, EXT0xx, no, sv/int_fp_mv, 1R1W1w, SFFS, TODO
-fmvfg(s),    ls006.fpintmv, high, 10, yes, EXT0xx, no, sv/int_fp_mv, 1R1W1w, SFFS, TODO
-fcvtfg(s),   ls006.fpintmv, high, 10, yes, EXT0xx, no, sv/int_fp_mv, 1R1W1w, SFFS, TODO
-fcvttg(o),   ls006.fpintmv, high, 9,  yes, EXT0xx, no, sv/int_fp_mv, 1R1W1w, SFFS, TODO
+mffpr(s),    ls006.fpintmv, high, 10, yes, EXT0xx, no, sv/int_fp_mv, 1R1W1w, SFFS, TODO
+mtfpr(s),    ls006.fpintmv, high, 10, yes, EXT0xx, no, sv/int_fp_mv, 1R1W1w, SFFS, TODO
+ctfpr(s),   ls006.fpintmv, high, 10, yes, EXT0xx, no, sv/int_fp_mv, 1R1W1w, SFFS, TODO
+cffpr(o),   ls006.fpintmv, high, 9,  yes, EXT0xx, no, sv/int_fp_mv, 1R1W1w, SFFS, TODO
 # Big-Integer Chained 3-in 2-out (64-bit Carry)
 dsld,        ls003.bignum, high, 5,  yes, EXT0xx, no, sv/biginteger, 3R2W1w, SFFS, yes
 dsrd,        ls003.bignum, high, 5,  yes, EXT0xx, no, sv/biginteger, 3R2W1w, SFFS, yes