fix incorrect statements about maddld

diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn
index 66874c690d64647ea42007ab4553ef63171c076e..ca6065eb035f370b0d45c1e8e62bf783eb33023d 100644 (file)
--- a/openpower/sv/biginteger.mdwn
+++ b/openpower/sv/biginteger.mdwn
@@ -90,8 +90,12 @@ to it; the lower half of that result stored in RT and the upper half
 in RS.
 
 The differences here to `maddhdu` are that `maddhdu` stores the upper
-half in RT, where `maddedu` stores the upper half in RS. There is no
-equivalent to `maddld` because `maddld` performs sign-extension on RC.
+half in RT, where `maddedu` stores the upper half in RS.
+
+The value stored in RT is exactly equivalent to `maddld` despite `maddld`
+performing sign-extension on RC, because RT is the full mathematical result
+modulo 2^64 and sign/zero extension from 64 to 128 bits produces identical
+results modulo 2^64. This is why there is no maddldu instruction.
 
 *Programmer's Note:
 As a Scalar Power ISA operation, like `lq` and `stq`, RS=RT+1.

diff --git a/openpower/sv/rfc/ls003.mdwn b/openpower/sv/rfc/ls003.mdwn
index 69384c3bf7df42065c1778062ba7c8b234c8e7ce..619d9d516b3a4d3d00b3afeadf6e5bf2471ade1f 100644 (file)
--- a/openpower/sv/rfc/ls003.mdwn
+++ b/openpower/sv/rfc/ls003.mdwn
@@ -108,8 +108,12 @@ to it; the lower half of that result stored in RT and the upper half
 in RS.
 
 The differences here to `maddhdu` are that `maddhdu` stores the upper
-half in RT, where `maddedu` stores the upper half in RS. There is **no
-equivalent to `maddld`** because `maddld` performs sign-extension on RC.
+half in RT, where `maddedu` stores the upper half in RS.
+
+The value stored in RT is exactly equivalent to `maddld` despite `maddld`
+performing sign-extension on RC, because RT is the full mathematical result
+modulo 2^64 and sign/zero extension from 64 to 128 bits produces identical
+results modulo 2^64. This is why there is no maddldu instruction.
 
 RS is implictly defined as the register following RT (RS=RT+1).