convert fcvtfg to fcvtfg[s][.]

diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn
index 713643a5fb66f51dd73242bfc52551c74f612e3a..34f0cf3aa0def16d1f08e2c7c15d6185e36b8a77 100644 (file)
--- a/openpower/sv/int_fp_mv.mdwn
+++ b/openpower/sv/int_fp_mv.mdwn
@@ -395,14 +395,17 @@ as exceptions.
 
 ## Floating-point Convert From GPR
 
-| 0-5 | 6-10 | 11-12 | 13-15 | 16-20 | 21-29 | 30-31 | Form   |
-|-----|------|-------|-------|-------|-------|-------|--------|
-| PO  | FRT  | IT    | 0     | RB    | XO    | RCS   | X-Form |
+| 0-5 | 6-10 | 11-12 | 13-15 | 16-20 | 21-30 | 31 | Form   |
+|-----|------|-------|-------|-------|-------|----|--------|
+| PO  | FRT  | IT    | 0     | RB    | XO    | Rc | X-Form |
 
-`fcvtfg FRT, RB, IT, RCS`
+`fcvtfg FRT, RB, IT`
+`fcvtfg. FRT, RB, IT`
+`fcvtfgs FRT, RB, IT`
+`fcvtfgs. FRT, RB, IT`
 
 ```
-    if IT[0] = 0 and RCS[0] = 0 then  # 32-bit int -> 64-bit float
+    if IT[0] = 0 then  # 32-bit int -> 64-bit float
         # rounding never necessary, so don't touch FPSCR
         # based off xvcvsxwdp
         if IT = 0 then  # Signed 32-bit
@@ -422,15 +425,9 @@ as exceptions.
                 src <- bfp_CONVERT_FROM_SI64((RB))
             default:  # Unsigned 64-bit
                 src <- bfp_CONVERT_FROM_UI64((RB))
-        if RCS[0] = 1 then  # Single
-            rnd <- bfp_ROUND_TO_BFP32(FPSCR.RN, src)
-            result32 <- bfp32_CONVERT_FROM_BFP(rnd)
-            cls <- fprf_CLASS_BFP32(result32)
-            result <- DOUBLE(result32)
-        else
-            rnd <- bfp_ROUND_TO_BFP64(FPSCR.RN, src)
-            result <- bfp64_CONVERT_FROM_BFP(rnd)
-            cls <- fprf_CLASS_BFP64(result)
+        rnd <- bfp_ROUND_TO_BFP64(FPSCR.RN, src)
+        result <- bfp64_CONVERT_FROM_BFP(rnd)
+        cls <- fprf_CLASS_BFP64(result)
 
         if xx_flag = 1 then SetFX(FPSCR.XX)
 
@@ -442,8 +439,9 @@ as exceptions.
 <!-- note the PowerISA spec. explicitly has empty lines before/after SetFX,
 don't remove them -->
 
-Convert from a unsigned/signed 32/64-bit integer in RB to a 32/64-bit
-float in FRT, following the usual 32-bit float in 64-bit float format.
+Convert from a unsigned/signed 32/64-bit integer in RB to a 64-bit
+float in FRT.
+
 If converting from a unsigned/signed 32-bit integer to a 64-bit float,
 rounding is never necessary, so `FPSCR` is unmodified and exceptions are
 never raised. Otherwise, `FPSCR` is modified and exceptions are raised
@@ -455,39 +453,27 @@ operations.
 Special Registers altered:
 
     CR1     (if Rc=1)
-    FPCSR   (TODO: which bits?) (if IT[0] != 0 or RCS[0] != 0)
+    FPCSR   (TODO: which bits?) (if IT[0]=1)
 
 ### Assembly Aliases
 
-| Assembly Alias       | Full Instruction       |&nbsp;| Assembly Alias       | Full Instruction       |
-|----------------------|------------------------|------|----------------------|------------------------|
-| `fcvtfgw FRT, RB`    | `fcvtfg FRT, RB, 0, 0` |&nbsp;| `fcvtfgd FRT, RB`    | `fcvtfg FRT, RB, 2, 0` |
-| `fcvtfgw. FRT, RB`   | `fcvtfg FRT, RB, 0, 1` |&nbsp;| `fcvtfgd. FRT, RB`   | `fcvtfg FRT, RB, 2, 1` |
-| `fcvtfgws FRT, RB`   | `fcvtfg FRT, RB, 0, 2` |&nbsp;| `fcvtfgds FRT, RB`   | `fcvtfg FRT, RB, 2, 2` |
-| `fcvtfgws. FRT, RB`  | `fcvtfg FRT, RB, 0, 3` |&nbsp;| `fcvtfgds. FRT, RB`  | `fcvtfg FRT, RB, 2, 3` |
-| `fcvtfguw FRT, RB`   | `fcvtfg FRT, RB, 1, 0` |&nbsp;| `fcvtfgud FRT, RB`   | `fcvtfg FRT, RB, 3, 0` |
-| `fcvtfguw. FRT, RB`  | `fcvtfg FRT, RB, 1, 1` |&nbsp;| `fcvtfgud. FRT, RB`  | `fcvtfg FRT, RB, 3, 1` |
-| `fcvtfguws FRT, RB`  | `fcvtfg FRT, RB, 1, 2` |&nbsp;| `fcvtfguds FRT, RB`  | `fcvtfg FRT, RB, 3, 2` |
-| `fcvtfguws. FRT, RB` | `fcvtfg FRT, RB, 1, 3` |&nbsp;| `fcvtfguds. FRT, RB` | `fcvtfg FRT, RB, 3, 3` |
+| Assembly Alias       | Full Instruction     |&nbsp;| Assembly Alias       | Full Instruction     |
+|----------------------|----------------------|------|----------------------|----------------------|
+| `fcvtfgw FRT, RB`    | `fcvtfg FRT, RB, 0`  |&nbsp;| `fcvtfgd FRT, RB`    | `fcvtfg FRT, RB, 2`  |
+| `fcvtfgw. FRT, RB`   | `fcvtfg. FRT, RB, 0` |&nbsp;| `fcvtfgd. FRT, RB`   | `fcvtfg. FRT, RB, 2` |
+| `fcvtfguw FRT, RB`   | `fcvtfg FRT, RB, 1`  |&nbsp;| `fcvtfgud FRT, RB`   | `fcvtfg FRT, RB, 3`  |
+| `fcvtfguw. FRT, RB`  | `fcvtfg. FRT, RB, 1` |&nbsp;| `fcvtfgud. FRT, RB`  | `fcvtfg. FRT, RB, 3` |
 
-## Floating-point Convert From GPR
+## Floating-point Convert From GPR Single
 
-| 0-5 | 6-10 | 11-12 | 13-15 | 16-20 | 21-29 | 30-31 | Form   |
-|-----|------|-------|-------|-------|-------|-------|--------|
-| PO  | FRT  | IT    | 0     | RB    | XO    | RCS   | X-Form |
+| 0-5 | 6-10 | 11-12 | 13-15 | 16-20 | 21-30 | 31 | Form   |
+|-----|------|-------|-------|-------|-------|----|--------|
+| PO  | FRT  | IT    | 0     | RB    | XO    | Rc | X-Form |
 
-`fcvtfg FRT, RB, IT, RCS`
+`fcvtfgs FRT, RB, IT`
+`fcvtfgs. FRT, RB, IT`
 
 ```
-    if IT[0] = 0 and RCS[0] = 0 then  # 32-bit int -> 64-bit float
-        # rounding never necessary, so don't touch FPSCR
-        # based off xvcvsxwdp
-        if IT = 0 then  # Signed 32-bit
-            src <- bfp_CONVERT_FROM_SI32((RB)[32:63])
-        else  # IT = 1 -- Unsigned 32-bit
-            src <- bfp_CONVERT_FROM_UI32((RB)[32:63])
-        FRT <- bfp64_CONVERT_FROM_BFP(src)
-    else
     # rounding may be necessary. based off xscvuxdsp
     reset_xflags()
     switch(IT)
@@ -499,15 +485,10 @@ Special Registers altered:
             src <- bfp_CONVERT_FROM_SI64((RB))
         default:  # Unsigned 64-bit
             src <- bfp_CONVERT_FROM_UI64((RB))
-    if RCS[0] = 1 then  # Single
-        rnd <- bfp_ROUND_TO_BFP32(FPSCR.RN, src)
-        result32 <- bfp32_CONVERT_FROM_BFP(rnd)
-        cls <- fprf_CLASS_BFP32(result32)
-        result <- DOUBLE(result32)
-    else
-        rnd <- bfp_ROUND_TO_BFP64(FPSCR.RN, src)
-        result <- bfp64_CONVERT_FROM_BFP(rnd)
-        cls <- fprf_CLASS_BFP64(result)
+    rnd <- bfp_ROUND_TO_BFP32(FPSCR.RN, src)
+    result32 <- bfp32_CONVERT_FROM_BFP(rnd)
+    cls <- fprf_CLASS_BFP32(result32)
+    result <- DOUBLE(result32)
 
     if xx_flag = 1 then SetFX(FPSCR.XX)
 
@@ -519,12 +500,9 @@ Special Registers altered:
 <!-- note the PowerISA spec. explicitly has empty lines before/after SetFX,
 don't remove them -->
 
-Convert from a unsigned/signed 32/64-bit integer in RB to a 32/64-bit
+Convert from a unsigned/signed 32/64-bit integer in RB to a 32-bit
 float in FRT, following the usual 32-bit float in 64-bit float format.
-If converting from a unsigned/signed 32-bit integer to a 64-bit float,
-rounding is never necessary, so `FPSCR` is unmodified and exceptions are
-never raised. Otherwise, `FPSCR` is modified and exceptions are raised
-as usual.
+`FPSCR` is modified and exceptions are raised as usual.
 
 Rc=1 tests FRT and sets CR1, exactly like all other Scalar Floating-Point
 operations.
@@ -532,20 +510,16 @@ operations.
 Special Registers altered:
 
     CR1     (if Rc=1)
-    FPCSR   (TODO: which bits?) (if IT[0] != 0 or RCS[0] != 0)
+    FPCSR   (TODO: which bits?)
 
 ### Assembly Aliases
 
-| Assembly Alias       | Full Instruction       |&nbsp;| Assembly Alias       | Full Instruction       |
-|----------------------|------------------------|------|----------------------|------------------------|
-| `fcvtfgw FRT, RB`    | `fcvtfg FRT, RB, 0, 0` |&nbsp;| `fcvtfgd FRT, RB`    | `fcvtfg FRT, RB, 2, 0` |
-| `fcvtfgw. FRT, RB`   | `fcvtfg FRT, RB, 0, 1` |&nbsp;| `fcvtfgd. FRT, RB`   | `fcvtfg FRT, RB, 2, 1` |
-| `fcvtfgws FRT, RB`   | `fcvtfg FRT, RB, 0, 2` |&nbsp;| `fcvtfgds FRT, RB`   | `fcvtfg FRT, RB, 2, 2` |
-| `fcvtfgws. FRT, RB`  | `fcvtfg FRT, RB, 0, 3` |&nbsp;| `fcvtfgds. FRT, RB`  | `fcvtfg FRT, RB, 2, 3` |
-| `fcvtfguw FRT, RB`   | `fcvtfg FRT, RB, 1, 0` |&nbsp;| `fcvtfgud FRT, RB`   | `fcvtfg FRT, RB, 3, 0` |
-| `fcvtfguw. FRT, RB`  | `fcvtfg FRT, RB, 1, 1` |&nbsp;| `fcvtfgud. FRT, RB`  | `fcvtfg FRT, RB, 3, 1` |
-| `fcvtfguws FRT, RB`  | `fcvtfg FRT, RB, 1, 2` |&nbsp;| `fcvtfguds FRT, RB`  | `fcvtfg FRT, RB, 3, 2` |
-| `fcvtfguws. FRT, RB` | `fcvtfg FRT, RB, 1, 3` |&nbsp;| `fcvtfguds. FRT, RB` | `fcvtfg FRT, RB, 3, 3` |
+| Assembly Alias       | Full Instruction     |&nbsp;| Assembly Alias       | Full Instruction     |
+|----------------------|----------------------|------|----------------------|----------------------|
+| `fcvtfgws FRT, RB`   | `fcvtfg FRT, RB, 0`  |&nbsp;| `fcvtfgds FRT, RB`   | `fcvtfg FRT, RB, 2`  |
+| `fcvtfgws. FRT, RB`  | `fcvtfg. FRT, RB, 0` |&nbsp;| `fcvtfgds. FRT, RB`  | `fcvtfg. FRT, RB, 2` |
+| `fcvtfguws FRT, RB`  | `fcvtfg FRT, RB, 1`  |&nbsp;| `fcvtfguds FRT, RB`  | `fcvtfg FRT, RB, 3`  |
+| `fcvtfguws. FRT, RB` | `fcvtfg. FRT, RB, 1` |&nbsp;| `fcvtfguds. FRT, RB` | `fcvtfg. FRT, RB, 3` |
 
 ## Floating-point to Integer Conversion Overview
 

diff --git a/openpower/sv/rfc/ls006.mdwn b/openpower/sv/rfc/ls006.mdwn
index adeac3d4fc14b1fdde596c158accd99087ac4089..733b7e92d9f210a8c12af654e2ff5ed2560c5ccf 100644 (file)
--- a/openpower/sv/rfc/ls006.mdwn
+++ b/openpower/sv/rfc/ls006.mdwn
@@ -243,14 +243,17 @@ Special Registers altered:
 
 ## Floating-point Convert From GPR
 
-| 0-5 | 6-10 | 11-12 | 13-15 | 16-20 | 21-29 | 30-31 | Form   |
-|-----|------|-------|-------|-------|-------|-------|--------|
-| PO  | FRT  | IT    | 0     | RB    | XO    | RCS   | X-Form |
+| 0-5 | 6-10 | 11-12 | 13-15 | 16-20 | 21-30 | 31 | Form   |
+|-----|------|-------|-------|-------|-------|----|--------|
+| PO  | FRT  | IT    | 0     | RB    | XO    | Rc | X-Form |
 
-`fcvtfg FRT, RB, IT, RCS`
+`fcvtfg FRT, RB, IT`
+`fcvtfg. FRT, RB, IT`
+`fcvtfgs FRT, RB, IT`
+`fcvtfgs. FRT, RB, IT`
 
 ```
-    if IT[0] = 0 and RCS[0] = 0 then  # 32-bit int -> 64-bit float
+    if IT[0] = 0 then  # 32-bit int -> 64-bit float
         # rounding never necessary, so don't touch FPSCR
         # based off xvcvsxwdp
         if IT = 0 then  # Signed 32-bit
@@ -270,15 +273,9 @@ Special Registers altered:
                 src <- bfp_CONVERT_FROM_SI64((RB))
             default:  # Unsigned 64-bit
                 src <- bfp_CONVERT_FROM_UI64((RB))
-        if RCS[0] = 1 then  # Single
-            rnd <- bfp_ROUND_TO_BFP32(FPSCR.RN, src)
-            result32 <- bfp32_CONVERT_FROM_BFP(rnd)
-            cls <- fprf_CLASS_BFP32(result32)
-            result <- DOUBLE(result32)
-        else
-            rnd <- bfp_ROUND_TO_BFP64(FPSCR.RN, src)
-            result <- bfp64_CONVERT_FROM_BFP(rnd)
-            cls <- fprf_CLASS_BFP64(result)
+        rnd <- bfp_ROUND_TO_BFP64(FPSCR.RN, src)
+        result <- bfp64_CONVERT_FROM_BFP(rnd)
+        cls <- fprf_CLASS_BFP64(result)
 
         if xx_flag = 1 then SetFX(FPSCR.XX)
 
@@ -290,8 +287,9 @@ Special Registers altered:
 <!-- note the PowerISA spec. explicitly has empty lines before/after SetFX,
 don't remove them -->
 
-Convert from a unsigned/signed 32/64-bit integer in RB to a 32/64-bit
-float in FRT, following the usual 32-bit float in 64-bit float format.
+Convert from a unsigned/signed 32/64-bit integer in RB to a 64-bit
+float in FRT.
+
 If converting from a unsigned/signed 32-bit integer to a 64-bit float,
 rounding is never necessary, so `FPSCR` is unmodified and exceptions are
 never raised. Otherwise, `FPSCR` is modified and exceptions are raised
@@ -303,43 +301,31 @@ operations.
 Special Registers altered:
 
     CR1     (if Rc=1)
-    FPCSR   (TODO: which bits?) (if IT[0] != 0 or RCS[0] != 0)
+    FPCSR   (TODO: which bits?) (if IT[0]=1)
 
 ### Assembly Aliases
 
-| Assembly Alias       | Full Instruction       |&nbsp;| Assembly Alias       | Full Instruction       |
-|----------------------|------------------------|------|----------------------|------------------------|
-| `fcvtfgw FRT, RB`    | `fcvtfg FRT, RB, 0, 0` |&nbsp;| `fcvtfgd FRT, RB`    | `fcvtfg FRT, RB, 2, 0` |
-| `fcvtfgw. FRT, RB`   | `fcvtfg FRT, RB, 0, 1` |&nbsp;| `fcvtfgd. FRT, RB`   | `fcvtfg FRT, RB, 2, 1` |
-| `fcvtfgws FRT, RB`   | `fcvtfg FRT, RB, 0, 2` |&nbsp;| `fcvtfgds FRT, RB`   | `fcvtfg FRT, RB, 2, 2` |
-| `fcvtfgws. FRT, RB`  | `fcvtfg FRT, RB, 0, 3` |&nbsp;| `fcvtfgds. FRT, RB`  | `fcvtfg FRT, RB, 2, 3` |
-| `fcvtfguw FRT, RB`   | `fcvtfg FRT, RB, 1, 0` |&nbsp;| `fcvtfgud FRT, RB`   | `fcvtfg FRT, RB, 3, 0` |
-| `fcvtfguw. FRT, RB`  | `fcvtfg FRT, RB, 1, 1` |&nbsp;| `fcvtfgud. FRT, RB`  | `fcvtfg FRT, RB, 3, 1` |
-| `fcvtfguws FRT, RB`  | `fcvtfg FRT, RB, 1, 2` |&nbsp;| `fcvtfguds FRT, RB`  | `fcvtfg FRT, RB, 3, 2` |
-| `fcvtfguws. FRT, RB` | `fcvtfg FRT, RB, 1, 3` |&nbsp;| `fcvtfguds. FRT, RB` | `fcvtfg FRT, RB, 3, 3` |
+| Assembly Alias       | Full Instruction     |&nbsp;| Assembly Alias       | Full Instruction     |
+|----------------------|----------------------|------|----------------------|----------------------|
+| `fcvtfgw FRT, RB`    | `fcvtfg FRT, RB, 0`  |&nbsp;| `fcvtfgd FRT, RB`    | `fcvtfg FRT, RB, 2`  |
+| `fcvtfgw. FRT, RB`   | `fcvtfg. FRT, RB, 0` |&nbsp;| `fcvtfgd. FRT, RB`   | `fcvtfg. FRT, RB, 2` |
+| `fcvtfguw FRT, RB`   | `fcvtfg FRT, RB, 1`  |&nbsp;| `fcvtfgud FRT, RB`   | `fcvtfg FRT, RB, 3`  |
+| `fcvtfguw. FRT, RB`  | `fcvtfg. FRT, RB, 1` |&nbsp;| `fcvtfgud. FRT, RB`  | `fcvtfg. FRT, RB, 3` |
 
 ----------
 
 \newpage{}
 
-## Floating-point Convert From GPR
+## Floating-point Convert From GPR Single
 
-| 0-5 | 6-10 | 11-12 | 13-15 | 16-20 | 21-29 | 30-31 | Form   |
-|-----|------|-------|-------|-------|-------|-------|--------|
-| PO  | FRT  | IT    | 0     | RB    | XO    | RCS   | X-Form |
+| 0-5 | 6-10 | 11-12 | 13-15 | 16-20 | 21-30 | 31 | Form   |
+|-----|------|-------|-------|-------|-------|----|--------|
+| PO  | FRT  | IT    | 0     | RB    | XO    | Rc | X-Form |
 
-`fcvtfg FRT, RB, IT, RCS`
+`fcvtfgs FRT, RB, IT`
+`fcvtfgs. FRT, RB, IT`
 
 ```
-    if IT[0] = 0 and RCS[0] = 0 then  # 32-bit int -> 64-bit float
-        # rounding never necessary, so don't touch FPSCR
-        # based off xvcvsxwdp
-        if IT = 0 then  # Signed 32-bit
-            src <- bfp_CONVERT_FROM_SI32((RB)[32:63])
-        else  # IT = 1 -- Unsigned 32-bit
-            src <- bfp_CONVERT_FROM_UI32((RB)[32:63])
-        FRT <- bfp64_CONVERT_FROM_BFP(src)
-    else
     # rounding may be necessary. based off xscvuxdsp
     reset_xflags()
     switch(IT)
@@ -351,15 +337,10 @@ Special Registers altered:
             src <- bfp_CONVERT_FROM_SI64((RB))
         default:  # Unsigned 64-bit
             src <- bfp_CONVERT_FROM_UI64((RB))
-    if RCS[0] = 1 then  # Single
-        rnd <- bfp_ROUND_TO_BFP32(FPSCR.RN, src)
-        result32 <- bfp32_CONVERT_FROM_BFP(rnd)
-        cls <- fprf_CLASS_BFP32(result32)
-        result <- DOUBLE(result32)
-    else
-        rnd <- bfp_ROUND_TO_BFP64(FPSCR.RN, src)
-        result <- bfp64_CONVERT_FROM_BFP(rnd)
-        cls <- fprf_CLASS_BFP64(result)
+    rnd <- bfp_ROUND_TO_BFP32(FPSCR.RN, src)
+    result32 <- bfp32_CONVERT_FROM_BFP(rnd)
+    cls <- fprf_CLASS_BFP32(result32)
+    result <- DOUBLE(result32)
 
     if xx_flag = 1 then SetFX(FPSCR.XX)
 
@@ -371,12 +352,9 @@ Special Registers altered:
 <!-- note the PowerISA spec. explicitly has empty lines before/after SetFX,
 don't remove them -->
 
-Convert from a unsigned/signed 32/64-bit integer in RB to a 32/64-bit
+Convert from a unsigned/signed 32/64-bit integer in RB to a 32-bit
 float in FRT, following the usual 32-bit float in 64-bit float format.
-If converting from a unsigned/signed 32-bit integer to a 64-bit float,
-rounding is never necessary, so `FPSCR` is unmodified and exceptions are
-never raised. Otherwise, `FPSCR` is modified and exceptions are raised
-as usual.
+`FPSCR` is modified and exceptions are raised as usual.
 
 Rc=1 tests FRT and sets CR1, exactly like all other Scalar Floating-Point
 operations.
@@ -384,20 +362,16 @@ operations.
 Special Registers altered:
 
     CR1     (if Rc=1)
-    FPCSR   (TODO: which bits?) (if IT[0] != 0 or RCS[0] != 0)
+    FPCSR   (TODO: which bits?)
 
 ### Assembly Aliases
 
-| Assembly Alias       | Full Instruction       |&nbsp;| Assembly Alias       | Full Instruction       |
-|----------------------|------------------------|------|----------------------|------------------------|
-| `fcvtfgw FRT, RB`    | `fcvtfg FRT, RB, 0, 0` |&nbsp;| `fcvtfgd FRT, RB`    | `fcvtfg FRT, RB, 2, 0` |
-| `fcvtfgw. FRT, RB`   | `fcvtfg FRT, RB, 0, 1` |&nbsp;| `fcvtfgd. FRT, RB`   | `fcvtfg FRT, RB, 2, 1` |
-| `fcvtfgws FRT, RB`   | `fcvtfg FRT, RB, 0, 2` |&nbsp;| `fcvtfgds FRT, RB`   | `fcvtfg FRT, RB, 2, 2` |
-| `fcvtfgws. FRT, RB`  | `fcvtfg FRT, RB, 0, 3` |&nbsp;| `fcvtfgds. FRT, RB`  | `fcvtfg FRT, RB, 2, 3` |
-| `fcvtfguw FRT, RB`   | `fcvtfg FRT, RB, 1, 0` |&nbsp;| `fcvtfgud FRT, RB`   | `fcvtfg FRT, RB, 3, 0` |
-| `fcvtfguw. FRT, RB`  | `fcvtfg FRT, RB, 1, 1` |&nbsp;| `fcvtfgud. FRT, RB`  | `fcvtfg FRT, RB, 3, 1` |
-| `fcvtfguws FRT, RB`  | `fcvtfg FRT, RB, 1, 2` |&nbsp;| `fcvtfguds FRT, RB`  | `fcvtfg FRT, RB, 3, 2` |
-| `fcvtfguws. FRT, RB` | `fcvtfg FRT, RB, 1, 3` |&nbsp;| `fcvtfguds. FRT, RB` | `fcvtfg FRT, RB, 3, 3` |
+| Assembly Alias       | Full Instruction     |&nbsp;| Assembly Alias       | Full Instruction     |
+|----------------------|----------------------|------|----------------------|----------------------|
+| `fcvtfgws FRT, RB`   | `fcvtfg FRT, RB, 0`  |&nbsp;| `fcvtfgds FRT, RB`   | `fcvtfg FRT, RB, 2`  |
+| `fcvtfgws. FRT, RB`  | `fcvtfg. FRT, RB, 0` |&nbsp;| `fcvtfgds. FRT, RB`  | `fcvtfg. FRT, RB, 2` |
+| `fcvtfguws FRT, RB`  | `fcvtfg FRT, RB, 1`  |&nbsp;| `fcvtfguds FRT, RB`  | `fcvtfg FRT, RB, 3`  |
+| `fcvtfguws. FRT, RB` | `fcvtfg. FRT, RB, 1` |&nbsp;| `fcvtfguds. FRT, RB` | `fcvtfg. FRT, RB, 3` |
 
 ----------