clarify

diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn
index 6882d388a91c0cead3cf02f41b766f4168de592f..135595a771efb106b7c16bfd99994e2383a74f18 100644 (file)
--- a/simple_v_extension.mdwn
+++ b/simple_v_extension.mdwn
@@ -448,14 +448,6 @@ This instead becomes an *indirect* reference using the *internal* state
 table generated from the Predication CSR key-value store, which iwws used
 as follows.
 
-Note:
-
-* d, s1 and s2 are booleans indicating whether destination,
-  source1 and source2 are vector or scalar
-* key-value CSR-redirection of rd, rs1 and rs2 have NOT been included
-  below, for clarity.  rd, rs1 and rs2 all also must ALSO go through
-  register-level redirection (from the Register CSR table) if they are vectors.
-
     if type(iop) == INT:
         preg = int_pred_reg[rd]
     else:
@@ -476,6 +468,15 @@ Note:
         else if (preg[rd].zero)
             // TODO: place zero in dest reg
 
+Note:
+
+* d, s1 and s2 are booleans indicating whether destination,
+  source1 and source2 are vector or scalar
+* key-value CSR-redirection of rd, rs1 and rs2 have NOT been included
+  below, for clarity.  rd, rs1 and rs2 all also must ALSO go through
+  register-level redirection (from the Register CSR table) if they are
+  vectors.
+
 ## MAXVECTORDEPTH
 
 MAXVECTORDEPTH is the same concept as MVL in RVV.  However in Simple-V,