(no commit message)

diff --git a/openpower/sv/rfc/ls012.mdwn b/openpower/sv/rfc/ls012.mdwn
index 1df953daa32f7f1b92ca9b0d6ed4144a4b63ba11..ea254a1eeef7e7edf27a3d016692c1ddffa8cab7 100644 (file)
--- a/openpower/sv/rfc/ls012.mdwn
+++ b/openpower/sv/rfc/ls012.mdwn
@@ -4,18 +4,22 @@
 * <https://bugs.libre-soc.org/show_bug.cgi?id=1051>
 * <https://bugs.libre-soc.org/show_bug.cgi?id=1052>
 
-The purpose of this RFC is to give a full list of the upcoming Scalar
-opcodes developed by Libre-SOC, formally agree a priority order on an itertive
-basis, which ones should be EXT022 Sandbox, which in EXT0xx, which in EXT2xx,
-and for IBM to get a clear picture of
-the Opcode Allocation needs.  As this is a Formal ISA RFC the evaluation
+The purpose of this RFC is:
+
+* to give a full list of the upcoming Scalar opcodes developed by Libre-SOC
+  (respecting that *all* of them are Vectoriseble)
+* formally agree a priority order on an itertive basis with new versions of this RFC,
+* which ones should be EXT022 Sandbox, which in EXT0xx, which in EXT2xx,
+* and for IBM to get a clear picture of the Opcode Allocation needs.
+
+As this is a Formal ISA RFC the evaluation
 shall ultimatly define (in advance of the actual submission of the instructions
-themselves) which instructions should be submitted over the next 18
+themselves) which instructions will be submitted over the next 8-18
 months.
 
 *It is expected that readers visit and interact with the Libre-SOC resources
 in order to do due-diligence on the prioritisation evaluation. Otherwise
-the ISA WG is overwhelmed by piecemeal RFCs that may turn out not
+the ISA WG is overwhelmed by "drip-fed" RFCs that may turn out not
 to be useful, against a background of having no guiding overview
 or pre-filtering, and everybody's precious time is wasted.
 Also note that the Libre-SOC Team, being funded by NLnet
@@ -35,8 +39,10 @@ IBM's primary focus has understandably been on PackedSIMD VSX.
 Unfortunately, with VSX being 914 instructions and 128-bit it is far too much for any
 new team to consider (10 years development effort) and far outside of
 Embedded or Tablet/Desktop/Laptop power budgets. Thus bringing Power Scalar
-up-to-date to modern standards is a reasonable goal, and the advantage is
-that lessons can be learned from other ISAs from the intervening years.
+up-to-date to modern standards *and on its own merits* is a reasonable goal,
+and the advantages of the reduced focus is that SFFS remains RISC-paradigm,
+and  that lessons can be learned from other ISAs from the intervening years.
+Good examples here include `bmask`.
 
 SVP64 Prefixing - also known by the terms "Zero-Overhead-Loop-Prefixing"
 as well as "True-Scalable-Vector Prefixing" - also literally brings new