(no commit message)

diff --git a/HDL_workflow/fpga.mdwn b/HDL_workflow/fpga.mdwn
index c258a4ef71b225df430268e3bdc6d978d0cefc11..a5d090a2695dcc20bf7f101310535ac467d2cb7e 100644 (file)
--- a/HDL_workflow/fpga.mdwn
+++ b/HDL_workflow/fpga.mdwn
@@ -49,8 +49,8 @@ and to end up learning the hard way by destroying the FPGA.
 Connecting the dots:
 
 
-litex platform file
-```litex-boards/litex_boards/platforms/ulx3s.py
+litex platform file litex-boards/litex_boards/platforms/ulx3s.py
+```
 ("gpio", 0,
     Subsignal("p", Pins("B11")),
     Subsignal("n", Pins("C11")),
@@ -63,16 +63,17 @@ litex platform file
 ),
 ```
 
-ulx3s contstraints file
-```github.com/emard/ulx3s/blob/master/doc/constraints/ulx3s_v20.lpf#L341-342
+ulx3s contstraints file github.com/emard/ulx3s/blob/master/doc/constraints/ulx3s_v20.lpf#L341-342
+```
 LOCATE COMP "gp[0]" SITE "B11"; # J1_5+  GP0 PCLK
 LOCATE COMP "gn[0]" SITE "C11"; # J1_5-  GN0 PCLK
 LOCATE COMP "gp[1]" SITE "A10"; # J1_7+  GP1 PCLK
 LOCATE COMP "gn[1]" SITE "A11"; # J1_7-  GN1 PCLK
 ```
 
-```https://github.com/emard/ulx3s/blob/master/doc/schematics_v308.pdf
+ULX3S FPGA Schematic https://github.com/emard/ulx3s/blob/master/doc/schematics_v308.pdf
 
+```
 J1 J2 PIN number 1-40 is for FEMALE 90° ANGLED header.
 For MALE VERTICAL header, SWAP EVEN and ODD pin numbers.