rewrite int/fp moves specification text to use style requested by luke

https://bugs.libre-soc.org/show_bug.cgi?id=1118#c1

diff --git a/openpower/sv/int_fp_mv/moves_and_conversions.mdwn b/openpower/sv/int_fp_mv/moves_and_conversions.mdwn
index 50a9d4288fb3746277dc5aca2c2649b82a926f60..9010a036d21ffb1fbdf5de948916450e1f1afd2a 100644 (file)
--- a/openpower/sv/int_fp_mv/moves_and_conversions.mdwn
+++ b/openpower/sv/int_fp_mv/moves_and_conversions.mdwn
@@ -33,8 +33,8 @@ Tables that are used by
 
 # Moves
 
-These instructions perform a straight unaltered bit-level copy from one Register
-File to another.
+These instructions perform a copy from one register file to another, as if by
+using a GPR/FPR store, followed by a FPR/GPR load.
 
 ## Move From FPR
 
@@ -51,14 +51,7 @@ File to another.
     RT <- (FRB)
 ```
 
-Move a 64-bit float from a FPR to a GPR, just copying bits of the IEEE 754
-representation directly. This is equivalent to `stfd` followed by `ld`.
-As `mffpr` is just copying bits, `FPSCR` is not affected in any way. `mffpr` is
-similar to `mfvsrd`, except doesn't require VSX, which is useful for SFFS
-implementations.
-
-Rc=1 tests RT and sets CR0, exactly like all other Scalar Fixed-Point
-operations.
+The contents of `FPR[FRB]` are placed into `GPR[RT]`.
 
 Special Registers altered:
 
@@ -66,6 +59,17 @@ Special Registers altered:
     CR0     (if Rc=1)
 ```
 
+Architecture Note:
+
+`mffpr` is equivalent to the combination of `stfd` followed by `ld`.
+
+Architecture Note:
+
+`mffpr` is a separate instruction from `mfvsrd` because `mfvsrd` requires
+VSX which may not be available on simpler implementations.
+Additionally, SVP64 may treat VSX instructions differently than SFFS
+instructions in a future version of the architecture.
+
 ----------
 
 ## Move From FPR Single
@@ -80,16 +84,11 @@ Special Registers altered:
 | PO  | RT   | //    | FRB   | XO    | Rc | X-Form |
 
 ```
-    RT <- [0] * 32 || SINGLE((FRB))  # SINGLE since that's what stfs uses
+    RT <- [0] * 32 || SINGLE((FRB))
 ```
 
-Move a BFP32 from a FPR to a GPR, by using `SINGLE` to extract the standard
-`BFP32` form from FRB and zero-extending the result to 64-bits and storing to
-RT. This is equivalent to `stfs` followed by `lwz`.
-As `mffprs` is just copying the BFP32 form, `FPSCR` is not affected in any way.
-
-Rc=1 tests RT and sets CR0, exactly like all other Scalar Fixed-Point
-operations.
+The contents of `FPR[FRB]` are converted to BFP32 by using `SINGLE`, then
+zero-extended to 64-bits, and the result stored in `GPR[RT]`.
 
 Special Registers altered:
 
@@ -97,6 +96,10 @@ Special Registers altered:
     CR0     (if Rc=1)
 ```
 
+Architecture Note:
+
+`mffprs` is equivalent to the combination of `stfs` followed by `lwz`.
+
 ----------
 
 \newpage{}
@@ -115,11 +118,7 @@ Special Registers altered:
     FRT <- (RB)
 ```
 
-move a 64-bit float from a GPR to a FPR, just copying bits of the IEEE 754
-representation directly. This is equivalent to `std` followed by `lfd`.
-As `mtfpr` is just copying bits, `FPSCR` is not affected in any way. `mtfpr` is
-similar to `mtvsrd`, except doesn't require VSX, which is useful for SFFS
-implementations.
+The contents of `GPR[RB]` are placed into `FPR[FRT]`.
 
 Special Registers altered:
 
@@ -127,6 +126,17 @@ Special Registers altered:
     None
 ```
 
+Architecture Note:
+
+`mtfpr` is equivalent to the combination of `std` followed by `lfd`.
+
+Architecture Note:
+
+`mtfpr` is a separate instruction from `mtvsrd` because `mtvsrd` requires
+VSX which may not be available on simpler implementations.
+Additionally, SVP64 may treat VSX instructions differently than SFFS
+instructions in a future version of the architecture.
+
 ----------
 
 ## Move To FPR Single
@@ -140,13 +150,11 @@ Special Registers altered:
 | PO  | FRT  | //    | RB    | XO    | // | X-Form |
 
 ```
-    FRT <- DOUBLE((RB)[32:63])  # DOUBLE since that's what lfs uses
+    FRT <- DOUBLE((RB)[32:63])
 ```
 
-Move a BFP32 from a GPR to a FPR, by using `DOUBLE` on the least significant
-32-bits of RB to do the standard BFP32 in BFP64 trick and store the result in
-FRT. This is equivalent to `stw` followed by `lfs`.
-As `mtfprs` is just copying the BFP32 form, `FPSCR` is not affected in any way.
+The contents of bits 32:63 of `GPR[RB]` are converted to BFP64 by using
+`DOUBLE`, then the result is stored in `GPR[RT]`.
 
 Special Registers altered:
 
@@ -154,6 +162,10 @@ Special Registers altered:
     None
 ```
 
+Architecture Note:
+
+`mtfprs` is equivalent to the combination of `stw` followed by `lfs`.
+
 ----------
 
 \newpage{}