slides update

diff --git a/shakti/m_class/libre_riscv_chennai_2018.tex b/shakti/m_class/libre_riscv_chennai_2018.tex
index eb0ee3a4cec1a7af89eab4add6add576126a1c26..91aa96060fdc358a93fb4b1cfb566a93899397a4 100644 (file)
--- a/shakti/m_class/libre_riscv_chennai_2018.tex
+++ b/shakti/m_class/libre_riscv_chennai_2018.tex
@@ -375,13 +375,27 @@
 }
 
 
-\frame{\frametitle{}
+\frame{\frametitle{Which Processor Cores to use?}
 
  \begin{itemize}
-   \item 
-   \item 
-   \item 
+   \item Shakti RV64 at the top of the list, not just for technical
+                reasons, but for the Shakti Group's goals and vision.
+          \vspace{6pt}
+   \item Libre 3D GPGPU (SMP RV64 plus accelerated custom ISA)
+            would make things interesting\\
+          (3D app pinned to a non-uniform but SMP architecture)
+          \vspace{6pt}
+   \item Video Processing again is reasonable to be a different
+            RV32/64 Core (SMP or otherwise), possibly not even RV
+            at all (MIPS, OR1200)
+          \vspace{6pt}
+   \item RV32 (PicoRV32?) always-on definitely needed (sleep mode)
+          \vspace{6pt}
   \end{itemize}
+  {\it Ultimately, decisions are flexible, heavily weighted
+          towards "what does good and doesn't do bad" as
+          well as cost vs risk
+  }
 }
 
 

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 902f7cc22a4ca9583b362fa488bdd1fff3d17c54..6401ef90baabb53b6331dc7c0ee80c93cd52f6df 100644 (file)
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -103,7 +103,7 @@
 \frame{\frametitle{What's the value of SV? Why adopt it even in non-V?}
 
  \begin{itemize}
-   \item memcpy becomes much smaller (higher bang-per-buck)
+   \item memcpy has a much higher bang-per-buck ratio
    \item context-switch (LOAD/STORE multiple): 1-2 instructions
    \item Compressed instrs further reduces I-cache (etc.)
    \item Reduced I-cache load (and less I-reads)
@@ -471,10 +471,10 @@ def get\_pred\_val(bool is\_fp\_op, int reg):
 \begin{semiverbatim}
 function op\_add(rd, rs1, rs2) # add not VADD!
   int i, id=0, irs1=0, irs2=0;
+  predval = get\_pred\_val(FALSE, rd);
   rd  = int\_vec[rd ].isvector ? int\_vec[rd ].regidx : rd;
   rs1 = int\_vec[rs1].isvector ? int\_vec[rs1].regidx : rs1;
   rs2 = int\_vec[rs2].isvector ? int\_vec[rs2].regidx : rs2;
-  predval = get\_pred\_val(FALSE, rd);
   for (i = 0; i < VL; i++)
     if (predval \& 1<<i) # predication uses intregs
        ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];