ls003: Added dsld, description needs checking and rework

diff --git a/openpower/sv/rfc/ls003.mdwn b/openpower/sv/rfc/ls003.mdwn
index f3be473dda5e4330ae6be71ef9d7df1b3d15479b..3948c36638616b4812d7043929c17a55ed11cd51 100644 (file)
--- a/openpower/sv/rfc/ls003.mdwn
+++ b/openpower/sv/rfc/ls003.mdwn
@@ -247,6 +247,47 @@ Examples:
 divmod2du r4, r0, r1, r2
 ```
 
+# Dynamic-Shift Left Doubleword
+
+`dsld RT,RA,RB,RC`
+
+|  0-5  | 6-10 | 11-15 | 16-20 | 21-25 | 26-30 | 31 | Form     |
+|-------|------|-------|-------|-------|-------|----|----------|
+| EXT04 | RT   |  RA   |  RB   |   RC  |  XO   | Rc | VA2-Form |
+
+Pseudo-code:
+
+    n <- (RB)[58:63]                        # Take lower 6-bits of RB for shift
+    v <- ROTL64((RA), n)                    # Rotate RA 64-bit left by n bits
+    mask <- MASK(64, 63-n)                  # 1's mask, set mask[64-n:63] to 0's
+    RT <- (v[0:63] & mask) | ((RC) & ¬mask) # Mask out bits
+    RS <- v[0:63] & ¬mask
+    overflow = 0
+    if RS != [0]*64:
+        overflow = 1
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)
+
+The contents of register RA are shifted left the number
+of bits specified by (RB) 58:63.
+**Please check if this is correct!!! This condition is taken
+from PowerISA spec page 253, definition of MASK128(x,y)!!!**
+A mask is generated having 0-bits from bit (64-n) through
+bit 63 and 1-bits elsewhere.
+
+The rotated data is ANDed with the generated mask, and ORed
+with contents of RC ANDed with inverted mask.
+The result is placed into register RT.
+
+Additionally, the rotated data is ANDed with inverted mask and
+placed into register RS. If value in RS is not all 0's, the
+overflow flag is raised.
+
+Similarly maddedu and divmod2du, dsld can be chained (using RC).
+
+
 \newpage{}
 
 # VA2-Form