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diff --git a/SFFS/gentoo_bootstrap.mdwn b/SFFS/gentoo_bootstrap.mdwn
index 1fd890097427ca9a4010be55d8205a4a83fd0c64..96d20f45de808dd3447fa1dc20957e01831ec810 100644 (file)
--- a/SFFS/gentoo_bootstrap.mdwn
+++ b/SFFS/gentoo_bootstrap.mdwn
@@ -93,7 +93,7 @@ To verify that our buildflags were applied by the build tools and respected by t
 This is not a perfect solution and the proper way would be either to:
 
 - Simulate an SFFS compliant chip running this code such as [Microwatt](https://libre-soc.org/HDL_workflow/microwatt/) (very time consuming)
-- Use a softcore FPGA core or ASIC of Microwatt / LibreSOC to run this code (doable, FPGA softcore in progress [link to bug](link))
+- Use a softcore FPGA core or ASIC of Microwatt / LibreSOC to run this code (doable, FPGA softcore in progress [in progress](https://bugs.libre-soc.org/show_bug.cgi?id=1037))
 - Use the finalized Libre-SOC chip (doable once it is ready)
 
 Also note that this only tests for a subset of VSX instructions at the moment, more will be added in the future, this is simply a quick test to run before attempting to run on simulation and/or a softcore as both can be somewhat time consuming. In other words, if this test gives any VSX instructions, don't attempt to run the code in simulation or a softcore to avoid wasting precious time.