reorg

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 6e1c4e5a8d0842c6a18915d63584113fc98b9af4..24605fd68cfef2766509fba485206db1a7b4a1e3 100644 (file)
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -472,11 +472,11 @@ for (i = 0; i < 16; i++) // 16 CSRs?
    tb[idx].regidx   = CSRpred[i].regidx  // indirection
    tb[idx].isvector = CSRpred[i].isvector
    tb[idx].packed   = CSRpred[i].packed  // SIMD or not
-   tb[idx].bank     = CSRpred[i].bank    // 0 (1=reserved)
+   tb[idx].bank     = CSRpred[i].bank    // 0 (1=rsvd)
 \end{semiverbatim}
 
  \begin{itemize}
-   \item All 64 (int and FP) Entries zero'd before setting
+   \item All 32 int (and 32 FP) entries zero'd before setup
    \item Might be a bit complex to set up (TBD)
   \end{itemize}