(no commit message)

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index 94daa39f745ed41c1517bfb41af9718cc54b4be7..b4d94e589f9ae4bcfaf84cd7a07281201ca25978 100644 (file)
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -22,12 +22,13 @@ Links:
 
 # Code to convert
 
-There are four projects:
+There are five projects:
 
 * TestIssuer (the HDL)
 * ISACaller (the python-based simulator)
 * power-gem5 (a cycle accurate simulator)
 * Microwatt (VHDL)
+* gcc and binutils
 
 Each of these needs to have SV augmentation, and the best way to
 do it is if they are all done at the same time, implementing the same
@@ -59,7 +60,7 @@ People coordinating different tasks. This doesn't mean exclusive work on these a
 * Cole:
 * Luke: ISACaller, python-assembler-generator-class
 * Tobias:
-* Alexandre: binutils-svp64-assembler
+* Alexandre: binutils-svp64-assembler and gcc
 * Paul: microwatt
 
 # Adding SV