(no commit message)
authorlkcl <lkcl@web>
Sat, 29 Jan 2022 23:30:03 +0000 (23:30 +0000)
committerIkiWiki <ikiwiki.info>
Sat, 29 Jan 2022 23:30:03 +0000 (23:30 +0000)
shakti/m_class/sdram.mdwn

index 3963d5743d9467af4ff8c9d46d5ee24e84162b85..54cb59c69875ad283f847c858bb02e5246c889d5 100644 (file)
@@ -3,4 +3,5 @@
 * <https://bitbucket.org/casl/c-class/src/3fba75dfbd0c64815eb8ec6dc965666812c44bae/src/peripherals/sdram/?at=master>
 * <https://opencores.org/projects/sdr_ctrl>
 * WIP <https://gitlab.com/jock_tanner/asceticore/-/blob/master/control.py#L24-31>
-* * simulation verilator https://github.com/ZipCPU/xulalx25soc/blob/master/bench/cpp/sdramsim.cpp
+* simulation verilator https://github.com/ZipCPU/xulalx25soc/blob/master/bench/cpp/sdramsim.cpp
+* breakout board for FPGA <https://rlx.sk/en/breakout-boards-shields/5155-sdram-board-b-waveshare-8mx16bit-sdram-h57v1262gtr.html>