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diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index a7d23f106c9dde54a80cab0781ef734a80c6d598..c1bb830c728b1e10a530c54f0addf0af2b04f3b3 100644 (file)
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -209,8 +209,6 @@ on context after decoding of the Scalar suffix:
 | Field Name | Field bits | Description                            |
 |------------|------------|----------------------------------------|
 | ELWIDTH       | `4:5`      | Element Width                       |
-| PACK          | `4`        | Pack  subvectors (sv.setvl only)     |
-| UNPACK        | `5`        |  Unpack subvectors (sv.setvl only    |
 | ELWIDTH_SRC   | `6:7`      | Element Width for Source      |
 | EXTRA         | `10:18`    | Register Extra encoding                |                          
 | MODE          | `19:23`    | changes Vector behaviour               |
@@ -218,8 +216,6 @@ on context after decoding of the Scalar suffix:
 * MODE changes the behaviour of the SV operation (result saturation, mapreduce)
 * SUBVL groups elements together into vec2, vec3, vec4 for use in 3D and Audio/Video DSP work
 * ELWIDTH and ELWIDTH_SRC overrides the instruction's destination and source operand width
-* PACK and UNPACK apply to Subvector structure packing: may only be
-  set by the `sv.setvl` instruction.
 * MASK (and MASK_SRC) and MASKMODE provide predication (two types of sources: scalar INT and Vector CR).
 * Bits 10 to 18 (EXTRA) are further decoded depending on the RM category for the instruction, which is determined only by decoding the Scalar 32 bit suffix.