+\begin{frame}[fragile]
+ \frametitle{Big-Integer Multiply on SVP64}
+ How can we use SVP64 to Multiply a 64-bit by a 256-bit integer?
+ \pause
+ \begin{itemize}
+ \item new instruction: \codeinline{maddedu RT, RA, RB, RC}
+ \pause
+ \item $64 \times 64 + 64 \rightarrow 128$-bit Multiply-Add
+ \pause
+ \item Semantics as used in this presentation (somewhat simplified):
+ \begin{codeenv}
+result = (RA * RB) + RC
+RT = LSB_HALF(result)
+RC = MSB_HALF(result)
+ \end{codeenv}
+ \end{itemize}
+\end{frame}
+
+\begin{frame}[fragile]
+ \frametitle{Big-Integer Multiply on SVP64}
+ How can we use SVP64 to Multiply a 64-bit by a 256-bit integer?
+ \pause
+ \begin{codeenv}
+# 64-bit input in r3
+# 256-bit input in r20-23
+# 320-bit output in r4-8
+setvl 0, 0, 4, 0, 1, 1 # makes stuff run 4 times
+li r8, 0 # clear carry register
+sv.maddedu *r4, r3, *r20, r8 # carrying multiply
+@\pause@
+# expands to:
+li r8, 0
+maddedu r4, r3, r20, r8
+maddedu r5, r3, r21, r8
+maddedu r6, r3, r22, r8
+maddedu r7, r3, r23, r8
+ \end{codeenv}
+\end{frame}
+