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diff --git a/openpower/sv/rfc/ls003.mdwn b/openpower/sv/rfc/ls003.mdwn
index 78154cd2d1f79e2d1548f3d138d00e43ef33a5e8..a43cfe6764a03c666cffc461930c7151fc102d07 100644 (file)
--- a/openpower/sv/rfc/ls003.mdwn
+++ b/openpower/sv/rfc/ls003.mdwn
@@ -61,15 +61,20 @@
 **Motivation**
 
 Similar to `maddhdu` and `maddld`, but allow for a big-integer rolling
-accumulation affect. As the second result location is implicitly defined as the register after the first result (RS=RT+1), the Scalar Register set can be used
-for vector computation.
-Similar to `divdeu`, and has similar advantages to `maddedu`. Modulo result is
-available with the quotient.
+accumulation affect: `RC` effectively becomes a 64-bit carry in chains
+of highly efficient loop-unrolled arbitrary-length big-integer operations.
+Similar to `divdeu`, and has similar advantages to `maddedu`,
+Modulo result is available with the quotient.
 
 **Notes and Observations**:
 
 1. There is no need for an Rc=1 variant as VA-Form is being used.
 2. There is no need for Special Registers as VA-Form is being used. 
+3. Both instructions have been present in Intel x86 for several decades.
+4. Neither instruction is present in VSX: these are 128/64 whereas
+   VSX is 128/128.
+5. `maddedu` and `divmod2du` are inverses of each other, including
+  when used for arbitrary-length big-integer arithmetic
 
 **Changes**