(no commit message)
authorcolepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0 <colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0@web>
Sun, 1 Nov 2020 22:23:40 +0000 (22:23 +0000)
committerIkiWiki <ikiwiki.info>
Sun, 1 Nov 2020 22:23:40 +0000 (22:23 +0000)
HDL_workflow/fpga.mdwn

index 47ffe9aa1583b184eee82c3bbe2d1092520289f0..d62fe95e5f98f6ed5dab9e928b24c422b6d95618 100644 (file)
@@ -151,7 +151,7 @@ and therefore have no value are marked with 'NOT'
 
 ## Images of wires on FPGA and on STLINKV2
 
-pic fpga                                     pic stlinkv2
+[[!img HDL_workflow/jtag_wires_ulx3s_fpga.jpg size="200x" ]] [[!img HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg size="400x" ]]                                    
 
 ## Questions