(no commit message)

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index 1ed3ff82f2037b1839a166856deddf31e4a08183..bf82f88cd383ffc3bae88fd4ac36f7c3c113f497 100644 (file)
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -20,6 +20,7 @@ Links:
 * <https://bugs.libre-soc.org/show_bug.cgi?id=587> setvl ancillary tasks
  (instruction form SVL-Form, field designations, pseudocode, SPR allocation)
 * <https://bugs.libre-soc.org/show_bug.cgi?id=615> agree sv assembly syntax
+* <https://bugs.libre-soc.org/show_bug.cgi?id=617> TestIssuer add single/twin Predication
 
 # Code to convert
 
@@ -184,9 +185,9 @@ TODO.  INTs, FPs, CRs, these all increase to 128.  Welcome To Vector ISAs.
 
 At the same time the `Rc=1` CR offsets normslly CR0 and CR1 for fixed and FP scalar may also be adjusted.
 
-## Single Predication
+## Single and Twin Predication
 
-TODO
+* <https://bugs.libre-soc.org/show_bug.cgi?id=617> TestIssuer 
 
 ## Element width overrides