projects / libreriscv.git / commitdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (from parent 1: 86917b6)
(no commit message)
authorlkcl <lkcl@web>
Wed, 11 Jul 2018 10:15:14 +0000 (11:15 +0100)
committerIkiWiki <ikiwiki.info>
Wed, 11 Jul 2018 10:15:14 +0000 (11:15 +0100)
shakti/m_class/DDR.mdwn patch | blob | history

diff --git a/shakti/m_class/DDR.mdwn b/shakti/m_class/DDR.mdwn
index 8607cddf11f0222e6a7dbf4e628f1e8e51691c27..ff76057b04a0e3def7da4abf57e1319400c8e7da 100644 (file)
--- a/shakti/m_class/DDR.mdwn
+++ b/shakti/m_class/DDR.mdwn
@@ -2,3 +2,4 @@
 
 * <https://github.com/enjoy-digital/litedram> - controller inc. DDR3 / LPDDR3
 * <https://www.ohwr.org/projects/ddr3-sp6-core/wiki/wiki> - CERN DDR3 ctrl
+* Symbiotic EDA: DDR3 PHY available for $300k.
http://libre-riscv.org ikiwiki