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diff --git a/openpower/sv/rfc/ls009.mdwn b/openpower/sv/rfc/ls009.mdwn
index 114008922e184f314aafc6c92801a60091872830..e490f3ba1b98a607ad95d8892151fb6da899c008 100644 (file)
--- a/openpower/sv/rfc/ls009.mdwn
+++ b/openpower/sv/rfc/ls009.mdwn
@@ -90,8 +90,6 @@ Add the following entries to:
 
 # REMAP <a name="remap" />
 
-* see [[sv/propagation]] for a future way to apply REMAP
-
 REMAP is an advanced form of Vector "Structure Packing" that
 provides hardware-level support for commonly-used *nested* loop patterns.
 For more general reordering an Indexed REMAP mode is available.
@@ -100,7 +98,11 @@ REMAP allows the usual vector loop `0..VL-1` to be "reshaped" (re-mapped)
 from a linear form to a 2D or 3D transposed form, or "offset" to permit
 arbitrary access to elements (when elwidth overrides are used),
 independently on each Vector src or dest
-register.
+register. Aside from Indexed REMAP this is entirely Hardware-accelerated
+reordering and consequently not costly in terms of register access. It
+will however place a burden on Multi-Issue systems but no more than if -
+exactly as if - the equivalent Scalar instructions were explicitly
+loop-unrolled without SVP64.
 
 The initial primary motivation of REMAP was for Matrix Multiplication, reordering of sequential
 data in-place: in-place DCT and FFT were easily justified given the
@@ -154,7 +156,8 @@ the purposes of storing intermediary calculations.  As these intermediary
 results are Deterministically computed they may be useful.
 Additionally, because the intermediate results are always written out
 it is possible to service Precise Interrupts without affecting latency
-(a common limitation of Vector ISAs).
+(a common limitation of Vector ISAs implementing explicit
+Parallel Reduction instructions).
 
 # Basic principle
 
@@ -189,9 +192,11 @@ The following illustrative example multiplies a 3x4 and a 5x3
 matrix to create
 a 5x4 result:
 
+```
     svshape 5, 4, 3, 0, 0
     svremap 15, 1, 2, 3, 0, 0, 0, 0
     sv.fmadds *0, *8, *16, *0
+```
 
 * svshape sets up the four SVSHAPE SPRS for a Matrix Schedule
 * svremap activates four out of five registers RA RB RC RT RS (15)
@@ -531,8 +536,7 @@ SVSHAPE is actively applied or not.
 
 # svremap instruction <a name="svremap"> </a>
 
-There is also a corresponding SVRM-Form for the svremap
-instruction which matches the above SPR:
+SVRM-Form:
 
     svremap SVme,mi0,mi1,mi2,mo0,mo2,pst
 
@@ -540,6 +544,27 @@ instruction which matches the above SPR:
 | --   | --   | -- | --  | --  | --  | --  | --   | ----  | ----- |
 | PO   | SVme |mi0 | mi1 | mi2 | mo0 | mo1 | pst  | rsvd  | XO    |
 
+SVRM-Form
+
+* svremap SVme,mi0,mi1,mi2,mo0,mo1,pst
+
+Pseudo-code:
+
+    # registers RA RB RC RT EA/FRS SVSHAPE0-3 indices
+    SVSTATE[32:33] <- mi0
+    SVSTATE[34:35] <- mi1
+    SVSTATE[36:37] <- mi2
+    SVSTATE[38:39] <- mo0
+    SVSTATE[40:41] <- mo1
+    # enable bit for RA RB RC RT EA/FRS
+    SVSTATE[42:46] <- SVme
+    # persistence bit (applies to more than one instruction)
+    SVSTATE[62] <- pst
+
+Special Registers Altered:
+
+    None
+
 # SHAPE Remapping SPRs
 
 There are four "shape" SPRs, SHAPE0-3, 32-bits in each,