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fix: fmvtg. changes CR0, not CR1
authorJacob Lifshay <programmerjake@gmail.com>
Thu, 23 Mar 2023 00:15:50 +0000 (17:15 -0700)
committerJacob Lifshay <programmerjake@gmail.com>
Thu, 23 Mar 2023 00:17:03 +0000 (17:17 -0700)
openpower/sv/int_fp_mv.mdwn patch | blob | history
openpower/sv/rfc/ls006.mdwn patch | blob | history

diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn
index 4e8f40bd93843b6b451763c1ee0df349bcc3f9d6..4fe3fab1fc0ca0249404e7783b111f52b21e95f5 100644 (file)
--- a/openpower/sv/int_fp_mv.mdwn
+++ b/openpower/sv/int_fp_mv.mdwn
@@ -314,7 +314,7 @@ operations.
 
 Special Registers altered:
 
-    CR1     (if Rc=1)
+    CR0     (if Rc=1)
 
 ### Assembly Aliases
 
diff --git a/openpower/sv/rfc/ls006.mdwn b/openpower/sv/rfc/ls006.mdwn
index 4bc744b0d69f62a0082a89a653a26fbe69012b07..e7da40e3239252f56e76238f4fb26a23d89c5f7f 100644 (file)
--- a/openpower/sv/rfc/ls006.mdwn
+++ b/openpower/sv/rfc/ls006.mdwn
@@ -153,7 +153,7 @@ operations.
 
 Special Registers altered:
 
-    CR1     (if Rc=1)
+    CR0     (if Rc=1)
 
 ### Assembly Aliases
 
http://libre-riscv.org ikiwiki