(no commit message)

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index 76b699d09255709bbddc63e3038b86952998bf10..a9595709c064242596626bd72a90e11ecc5fbbaa 100644 (file)
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -121,12 +121,6 @@ Additional pseudo-op for obtaining VL without modifying it (or any state):
     getvl  r5      : setvl  r5, r0, vf=0, vs=0, ms=0
     getvl. r5      : setvl. r5, r0, vf=0, vs=0, ms=0
 
-For Vertical-First mode, a pseudo-op for explicit incrementing
-of srcstep and dststep:
-
-    svfstep         : setvl  0, 0, vf=1, vs=0, ms=0
-    svfstep.        : setvl. 0, 0, vf=1, vs=0, ms=0
-
 This pseudocode op is different from [[sv/svstep]] which is used to
 perform detailed enquiries about internal state.
 
@@ -163,47 +157,6 @@ Additionally, in reality it is **`VL`** being set. Therefore, rather
 than `CR0` testing `RT` when `Rc=1`, CR0.EQ is set if `VL=0`, CR0.GE
 is set if `VL` is non-zero.
 
-# Vertical First Mode
-
-Vertical First is effectively like an implicit single bit predicate
-applied to every SVP64 instruction.  **ONLY** one element in each
-SVP64 Vector instruction is executed; srcstep and dststep do **not**
-increment, and the Program Counter progresses **immediately** to
-the next instruction just as it would for any standard scalar v3.0B
-instruction.
-
-An explicit mode of setvl is called which can move srcstep and
-dststep on to the next element, still respecting predicate
-masks.  
-
-In other words, where normal SVP64 Vectorisation acts "horizontally"
-by looping first through 0 to VL-1 and only then moving the PC
-to the next instruction, Vertical-First moves the PC onwards
-(vertically) through multiple instructions **with the same
-srcstep and dststep**, then an explict instruction used to
-advance srcstep/dststep. An outer loop is expected to be
-used (branch instruction) which completes a series of
-Vector operations.
-
-```svfstep``` mode is enabled when vf=1, vs=0 and ms=0. 
-When Rc=1 it is possible to determine when any level of
-loops reach an end condition, or if VL has been reached. The immediate can
-be reinterpreted as indicating which SVSTATE (0-3)
-should be tested and placed into CR0 (when Rc=1)
-
-When RT is not zero, an internal stepping index may also be returned,
-either the REMAP index or srcstep or dststep. This table is identical
-to that of [[sv/svstep]]:
-
-* `SVi=1`: also include inner middle and outer
-  loop end conditions from SVSTATE0 into CR.EQ CR.LE CR.GT
-* `SVi=2`: test SVSTATE1 (and return conditions)
-* `SVi=3`: test SVSTATE2 (and return conditions)
-* `SVi=4`: test SVSTATE3 (and return conditions)
-* `SVi=5`: `SVSTATE.srcstep` is returned.
-* `SVi=6`: `SVSTATE.dststep` is returned.
-
-Testing any end condition of any loop of any REMAP state allows branches to be used to create loops.
 
 *Programmers should be aware that VL, srcstep and dststep are global in nature.
 Nested looping with different schedules is perfectly possible, as is