duplicate fmv[f/t]g sections in preperation for splitting out Single versions

diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn
index 4fe3fab1fc0ca0249404e7783b111f52b21e95f5..abebc500423003f47fdce9af8078bdf51bb99027 100644 (file)
--- a/openpower/sv/int_fp_mv.mdwn
+++ b/openpower/sv/int_fp_mv.mdwn
@@ -312,6 +312,33 @@ copying bits, `FPSCR` is not affected in any way.
 Rc=1 tests RT and sets CR0, exactly like all other Scalar Fixed-Point
 operations.
 
+Special Registers altered:
+
+    CR0     (if Rc=1)
+
+## FPR to GPR move
+
+`fmvtg RT, FRB, RCS`
+
+| 0-5 | 6-10 | 11-15 | 16-20 | 21-29 | 30-31 | Form   |
+|-----|------|-------|-------|-------|-------|--------|
+| PO  | RT   | 0     | FRB   | XO    | RCS   | X-Form |
+
+```
+    if RCS[0] = 1 then  # if Single mode
+        RT <- [0] * 32 || SINGLE((FRB))  # SINGLE since that's what stfs uses
+    else
+        RT <- (FRB)
+```
+
+Move a 32/64-bit float from a FPR to a GPR, just copying bits of the
+IEEE 754 representation directly. This is equivalent to `stfs` followed
+by `lwz` or equivalent to `stfd` followed by `ld`.  As `fmvtg` is just
+copying bits, `FPSCR` is not affected in any way.
+
+Rc=1 tests RT and sets CR0, exactly like all other Scalar Fixed-Point
+operations.
+
 Special Registers altered:
 
     CR0     (if Rc=1)
@@ -348,6 +375,33 @@ or equivalent to `std` followed by `lfd`. As `fmvfg` is just copying bits,
 Rc=1 tests FRT and sets CR1, exactly like all other Scalar Floating-Point
 operations.
 
+Special Registers altered:
+
+    CR1     (if Rc=1)
+
+## GPR to FPR move
+
+`fmvfg FRT, RB, RCS`
+
+| 0-5 | 6-10 | 11-15 | 16-20 | 21-29 | 30-31 | Form   |
+|-----|------|-------|-------|-------|-------|--------|
+| PO  | FRT  | 0     | RB    | XO    | RCS   | X-Form |
+
+```
+    if RCS[0] = 1 then  # if Single mode
+        FRT <- DOUBLE((RB)[32:63])  # DOUBLE since that's what lfs uses
+    else
+        FRT <- (RB)
+```
+
+move a 32/64-bit float from a GPR to a FPR, just copying bits of the IEEE
+754 representation directly. This is equivalent to `stw` followed by `lfs`
+or equivalent to `std` followed by `lfd`. As `fmvfg` is just copying bits,
+`FPSCR` is not affected in any way.
+
+Rc=1 tests FRT and sets CR1, exactly like all other Scalar Floating-Point
+operations.
+
 Special Registers altered:
 
     CR1     (if Rc=1)

diff --git a/openpower/sv/rfc/ls006.mdwn b/openpower/sv/rfc/ls006.mdwn
index e7da40e3239252f56e76238f4fb26a23d89c5f7f..4424be97c412c013a56818c2eb4793c4b30de159 100644 (file)
--- a/openpower/sv/rfc/ls006.mdwn
+++ b/openpower/sv/rfc/ls006.mdwn
@@ -124,6 +124,38 @@ Tables that are used by `fmvtg`/`fmvfg`/`fcvttg`/`fcvtfg`:
 [Java/Saturating semantics]: #fp-to-int-java-saturating-conversion-semantics
 [JavaScript semantics]: #fp-to-int-javascript-conversion-semantics
 
+----------
+
+\newpage{}
+
+## FPR to GPR move
+
+`fmvtg RT, FRB, RCS`
+
+| 0-5 | 6-10 | 11-15 | 16-20 | 21-29 | 30-31 | Form   |
+|-----|------|-------|-------|-------|-------|--------|
+| PO  | RT   | 0     | FRB   | XO    | RCS   | X-Form |
+
+```
+    if RCS[0] = 1 then  # if Single mode
+        RT <- [0] * 32 || SINGLE((FRB))  # SINGLE since that's what stfs uses
+    else
+        RT <- (FRB)
+```
+
+Move a 32/64-bit float from a FPR to a GPR, just copying bits of the
+IEEE 754 representation directly. This is equivalent to `stfs` followed
+by `lwz` or equivalent to `stfd` followed by `ld`.  As `fmvtg` is just
+copying bits, `FPSCR` is not affected in any way.
+
+Rc=1 tests RT and sets CR0, exactly like all other Scalar Fixed-Point
+operations.
+
+Special Registers altered:
+
+    CR0     (if Rc=1)
+
+
 ----------
 
 \newpage{}
@@ -165,6 +197,37 @@ Special Registers altered:
 | `fmvtgs. RT, FRB` | `fmvtg RT, FRB, 3` |
 
 
+----------
+
+\newpage{}
+
+## GPR to FPR move
+
+`fmvfg FRT, RB, RCS`
+
+| 0-5 | 6-10 | 11-15 | 16-20 | 21-29 | 30-31 | Form   |
+|-----|------|-------|-------|-------|-------|--------|
+| PO  | FRT  | 0     | RB    | XO    | RCS   | X-Form |
+
+```
+    if RCS[0] = 1 then  # if Single mode
+        FRT <- DOUBLE((RB)[32:63])  # DOUBLE since that's what lfs uses
+    else
+        FRT <- (RB)
+```
+
+move a 32/64-bit float from a GPR to a FPR, just copying bits of the IEEE
+754 representation directly. This is equivalent to `stw` followed by `lfs`
+or equivalent to `std` followed by `lfd`. As `fmvfg` is just copying bits,
+`FPSCR` is not affected in any way.
+
+Rc=1 tests FRT and sets CR1, exactly like all other Scalar Floating-Point
+operations.
+
+Special Registers altered:
+
+    CR1     (if Rc=1)
+
 ----------
 
 \newpage{}