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diff --git a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
index a6d7f78cef61f8cd5e039d60060d3b50017fc106..4cabb93bbbf69040396667f67841a6ad587446c7 100644 (file)
--- a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
+++ b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
@@ -2,40 +2,40 @@
 
 ## Register file
 
-| Register           | Andes ISA                    | Harmonised RVP ISA        |
-| ------------------ | -------------------------    | -------------------       |
-| v0                 | Hardwired zero               | Hardwired zero            |
-| v1                 | 32bit GPR or Vector[4xB|2xH] | Predicate masks           |
-| v2                 | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[4xSB] |
-| v3                 | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[4xSB] |
-| v4                 | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[4xSB] |
-| v5                 | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[4xSB] |
-| v6                 | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[4xSB] |
-| v7                 | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[4xSB] |
-| v8                 | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[4xUB] |
-| v9                 | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[4xUB] |
-| v10                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[4xUB] |
-| v11                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[4xUB] |
-| v12                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[4xUB] |
-| v13                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[4xUB] |
-| v14                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[4xUB] |
-| v15                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[4xUB] |
-| v16                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[2xSH] |
-| v17                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[2xSH] |
-| v18                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[2xSH] |
-| v19                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[2xSH] |
-| v20                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[2xSH] |
-| v21                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[2xSH] |
-| v22                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[2xSH] |
-| v23                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[2xSH] |
-| v24                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[2xUH] |
-| v25                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[2xUH] |
-| v26                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[2xUH] |
-| v27                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[2xUH] |
-| v28                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[2xUH] |
-| v29                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[2xUH] |
-| v30                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[1xUW] |
-| v31                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[1xUW] |
+| Register           | Andes ISA                       | Harmonised RVP ISA        |
+| ------------------ | -------------------------       | -------------------       |
+| v0                 | Hardwired zero                  | Hardwired zero            |
+| v1                 | 32bit GPR or Vector[4xB or 2xH] | Predicate masks           |
+| v2                 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[4xSB] |
+| v3                 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[4xSB] |
+| v4                 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[4xSB] |
+| v5                 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[4xSB] |
+| v6                 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[4xSB] |
+| v7                 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[4xSB] |
+| v8                 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[4xUB] |
+| v9                 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[4xUB] |
+| v10                | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[4xUB] |
+| v11                | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[4xUB] |
+| v12                | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[4xUB] |
+| v13                | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[4xUB] |
+| v14                | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[4xUB] |
+| v15                | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[4xUB] |
+| v16                | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[2xSH] |
+| v17                | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[2xSH] |
+| v18                | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[2xSH] |
+| v19                | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[2xSH] |
+| v20                | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[2xSH] |
+| v21                | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[2xSH] |
+| v22                | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[2xSH] |
+| v23                | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[2xSH] |
+| v24                | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[2xUH] |
+| v25                | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[2xUH] |
+| v26                | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[2xUH] |
+| v27                | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[2xUH] |
+| v28                | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[2xUH] |
+| v29                | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[2xUH] |
+| v30                | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[1xUW] |
+| v31                | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[1xUW] |