(no commit message)

diff --git a/HDL_workflow/ECP5_FPGA.mdwn b/HDL_workflow/ECP5_FPGA.mdwn
index 11134812a36b0933bd559c8427d09ff1bd228719..efb2b852311d1ab0b8d81ed60fc4b3709c074b9e 100644 (file)
--- a/HDL_workflow/ECP5_FPGA.mdwn
+++ b/HDL_workflow/ECP5_FPGA.mdwn
@@ -55,6 +55,8 @@ Follow this section if you have the Versa ECP5 FPGA:
 
 Final steps for both FPGA boards:
 
+| Done?   | Checklist Step |
+|---------|----------------|
 |         | Check each jumper wire connection between the corresponding pins on the FPGA and the STLINKv2 **four** times |
 |         | I don't know what's next, need to review with lkcl |