update README.txt to add extra notes
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 11 Sep 2021 14:37:46 +0000 (15:37 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 11 Sep 2021 14:37:46 +0000 (15:37 +0100)
README.txt

index 2cab663850af1c530d852f948bf79e5795bb7e2a..56adddf762d1ef5673a41e3fca87acd9263c9a34 100644 (file)
@@ -1,11 +1,15 @@
 # sim openocd test
 
-create verilog file "python issuer_verilog libresoc.v"
+in the soc directory, create the verilog file
+    "python issuer_verilog.py libresoc.v"
+
 copy to libresoc/ directory
 terminal 1: ./sim.py
 terminal 2: openocd -f openocd.cfg -c init -c 'svf idcode_test2.svf'
 
 # ecp5 build
 
+same thing: first build libresoc.v and copy it to the libresoc/ directory
+
 ./versa_ecp5.py --sys-clk-freq=55e6 --build
 ./versa_ecp5.py --sys-clk-freq=55e6 --load