add orangecrab uart and toolchain

diff --git a/src/ls2.py b/src/ls2.py
index cc55d1998fadbc5c0b395050d98f0e00dc901a36..e76d193efd7be9b28e0d6b26640af4cd3b1f6d99 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -16,7 +16,7 @@ from nmigen.lib.cdc import ResetSynchronizer
 from nmigen_soc import wishbone, memory
 from nmigen_soc.memory import MemoryMap
 from nmigen.utils import log2_int
-
+from nmigen_boards.resources.interface import UARTResource
 from nmigen_stdio.serial import AsyncSerial
 
 # HyperRAM
@@ -57,6 +57,7 @@ from nmigen_boards.versa_ecp5 import VersaECP5Platform85 # custom board
 from nmigen_boards.ulx3s import ULX3S_85F_Platform
 from nmigen_boards.arty_a7 import ArtyA7_100Platform
 from nmigen_boards.test.blinky import Blinky
+from nmigen_boards.orangecrab_r0_2 import OrangeCrabR0_2_85k_Platform
 from icarusversa import IcarusVersaPlatform
 # Clock-Reset Generator (works for all ECP5 platforms)
 from ecp5_crg import ECP5CRG
@@ -705,6 +706,7 @@ def build_platform(fpga, firmware):
     platform_kls =  {'versa_ecp5': VersaECP5Platform,
                      'versa_ecp5_85': VersaECP5Platform85,
                      'ulx3s': ULX3S_85F_Platform,
+                     'orangecrab': OrangeCrabR0_2_85k_Platform,
                      'arty_a7': ArtyA7_100Platform,
                      'isim': IcarusVersaPlatform,
                      'sim': None,
@@ -712,6 +714,7 @@ def build_platform(fpga, firmware):
     toolchain = {'arty_a7': "yosys_nextpnr",
                  'versa_ecp5': 'Trellis',
                  'versa_ecp5_85': 'Trellis',
+                 'orangecrab': 'Trellis',
                  'isim': 'Trellis',
                  'ulx3s': 'Trellis',
                  'sim': None,
@@ -759,6 +762,11 @@ def build_platform(fpga, firmware):
 
     # get UART resource pins
     if platform is not None:
+        if fpga=="orangecrab":
+            orangecrab_uart = UARTResource(0, rx="N17", tx="M18",
+                                attrs=Attrs(IOSTANDARD="LVCMOS33"))
+            platform.add_resources([orangecrab_uart])
+
         uart_pins = platform.request("uart", 0)
     else:
         uart_pins = Record([('tx', 1), ('rx', 1)], name="uart_0")