set dram_clk_freq = 100.0e6 for orangecrab

diff --git a/src/ls2.py b/src/ls2.py
index 53c379252f4f6d64db3d329704652b4b0c7cc3e6..f1efb8f58b784879db2cd9b19f14545043830d60 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -876,7 +876,7 @@ def build_platform(fpga, firmware):
         clk_freq = 40.0e6
     if fpga == 'orangecrab':
         clk_freq = 40.0e6 # 50 MHz does not work
-        ##dram_clk_freq = 80.0e6 # does not work yet (0 warnings, 2 errors)
+        dram_clk_freq = 100.0e6 # does not work yet (0 warnings, 2 errors)
 
     # merge dram_clk_freq with clk_freq if the same
     if clk_freq == dram_clk_freq: