Makefile

   1 GHDL ?= ghdl
   2 GHDLFLAGS=--std=08
   3 CFLAGS=-O3 -Wall
   4 VERILATOR_FLAGS=-O3 #--trace
   5 # It takes forever to build with optimisation, so disable by default
   6 #VERILATOR_CFLAGS=-O3
   7
   8 GHDLSYNTH ?= ghdl.so
   9 YOSYS     ?= yosys
  10 NEXTPNR   ?= nextpnr-ecp5
  11 ECPPACK   ?= ecppack
  12 OPENOCD   ?= openocd
  13
  14 # We need a version of GHDL built with either the LLVM or gcc backend.
  15 # Fedora provides this, but other distros may not. Another option is to use
  16 # the Docker image.
  17 DOCKER ?= 0
  18 PODMAN ?= 0
  19
  20 ifeq ($(DOCKER), 1)
  21 DOCKERBIN=docker
  22 USE_DOCKER=1
  23 endif
  24
  25 ifeq ($(PODMAN), 1)
  26 DOCKERBIN=podman
  27 USE_DOCKER=1
  28 endif
  29
  30 ifeq ($(USE_DOCKER), 1)
  31 PWD = $(shell pwd)
  32 DOCKERARGS = run --rm -v $(PWD):/src:z -w /src
  33 GHDL      = $(DOCKERBIN) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 ghdl
  34 CC        = $(DOCKERBIN) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 gcc
  35 GHDLSYNTH = ghdl
  36 YOSYS     = $(DOCKERBIN) $(DOCKERARGS) hdlc/ghdl:yosys yosys
  37 NEXTPNR   = $(DOCKERBIN) $(DOCKERARGS) hdlc/nextpnr:ecp5 nextpnr-ecp5
  38 ECPPACK   = $(DOCKERBIN) $(DOCKERARGS) hdlc/prjtrellis ecppack
  39 OPENOCD   = $(DOCKERBIN) $(DOCKERARGS) --device /dev/bus/usb hdlc/prog openocd
  40 endif
  41
  42 all = core_tb icache_tb dcache_tb multiply_tb dmi_dtm_tb divider_tb \
  43         rotator_tb countzero_tb wishbone_bram_tb soc_reset_tb
  44
  45 all: $(all)
  46
  47 core_files = decode_types.vhdl common.vhdl wishbone_types.vhdl fetch1.vhdl \
  48         utils.vhdl plru.vhdl cache_ram.vhdl icache.vhdl \
  49         decode1.vhdl helpers.vhdl insn_helpers.vhdl \
  50         control.vhdl decode2.vhdl register_file.vhdl \
  51         cr_file.vhdl crhelpers.vhdl ppc_fx_insns.vhdl rotator.vhdl \
  52         logical.vhdl countzero.vhdl multiply.vhdl divider.vhdl execute1.vhdl \
  53         loadstore1.vhdl mmu.vhdl dcache.vhdl writeback.vhdl core_debug.vhdl \
  54         core.vhdl fpu.vhdl
  55
  56 soc_files = wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_fifo.vhdl \
  57         wishbone_debug_master.vhdl xics.vhdl syscon.vhdl soc.vhdl \
  58         spi_rxtx.vhdl spi_flash_ctrl.vhdl
  59
  60 uart_files = $(wildcard uart16550/*.v)
  61
  62 soc_sim_files = $(core_files) $(soc_files) sim_console.vhdl sim_pp_uart.vhdl sim_bram_helpers.vhdl \
  63         sim_bram.vhdl sim_jtag_socket.vhdl sim_jtag.vhdl dmi_dtm_xilinx.vhdl \
  64         sim_16550_uart.vhdl \
  65         random.vhdl glibc_random.vhdl glibc_random_helpers.vhdl
  66
  67 soc_sim_c_files = sim_vhpi_c.c sim_bram_helpers_c.c sim_console_c.c \
  68         sim_jtag_socket_c.c
  69
  70 soc_sim_obj_files=$(soc_sim_c_files:.c=.o)
  71 comma := ,
  72 soc_sim_link=$(patsubst %,-Wl$(comma)%,$(soc_sim_obj_files))
  73
  74 unisim_dir = sim-unisim
  75 unisim_lib = $(unisim_dir)/unisim-obj08.cf
  76 unisim_lib_files = $(unisim_dir)/BSCANE2.vhdl $(unisim_dir)/BUFG.vhdl \
  77         $(unisim_dir)/unisim_vcomponents.vhdl
  78 $(unisim_lib): $(unisim_lib_files)
  79         $(GHDL) -i --std=08 --work=unisim --workdir=$(unisim_dir) $^
  80 GHDLFLAGS += -P$(unisim_dir)
  81
  82 core_tbs = multiply_tb divider_tb rotator_tb countzero_tb
  83 soc_tbs = core_tb icache_tb dcache_tb dmi_dtm_tb wishbone_bram_tb
  84 soc_flash_tbs = core_flash_tb
  85 soc_dram_tbs = dram_tb core_dram_tb
  86
  87 ifneq ($(FLASH_MODEL_PATH),)
  88 fmf_dir = $(FLASH_MODEL_PATH)/fmf
  89 fmf_lib = $(fmf_dir)/fmf-obj08.cf
  90 fmf_lib_files = $(wildcard $(fmf_dir)/*.vhd)
  91 GHDLFLAGS += -P$(fmf_dir)
  92 $(fmf_lib): $(fmf_lib_files)
  93         $(GHDL) -i --std=08 --work=fmf --workdir=$(fmf_dir) $^
  94
  95 flash_model_files=$(FLASH_MODEL_PATH)/s25fl128s.vhd
  96 flash_model_files: $(fmf_lib)
  97 else
  98 flash_model_files=sim_no_flash.vhdl
  99 fmf_lib=
 100 endif
 101
 102 $(soc_flash_tbs): %: $(soc_sim_files) $(soc_sim_obj_files) $(unisim_lib) $(fmf_lib) $(flash_model_files) %.vhdl
 103         $(GHDL) -c $(GHDLFLAGS) $(soc_sim_link) $(soc_sim_files) $(flash_model_files) $@.vhdl $(unisim_files) -e $@
 104
 105 $(soc_tbs): %: $(soc_sim_files) $(soc_sim_obj_files) $(unisim_lib) %.vhdl
 106         $(GHDL) -c $(GHDLFLAGS) $(soc_sim_link) $(soc_sim_files) $@.vhdl -e $@
 107
 108 $(core_tbs): %: $(core_files) glibc_random.vhdl glibc_random_helpers.vhdl %.vhdl
 109         $(GHDL) -c $(GHDLFLAGS) $(core_files) glibc_random.vhdl glibc_random_helpers.vhdl $@.vhdl -e $@
 110
 111 soc_reset_tb: fpga/soc_reset_tb.vhdl fpga/soc_reset.vhdl
 112         $(GHDL) -c $(GHDLFLAGS) fpga/soc_reset_tb.vhdl fpga/soc_reset.vhdl -e $@
 113
 114 # LiteDRAM sim
 115 VERILATOR_ROOT=$(shell verilator -getenv VERILATOR_ROOT 2>/dev/null)
 116 ifeq (, $(VERILATOR_ROOT))
 117 $(soc_dram_tbs):
 118         $(error "Verilator is required to make this target !")
 119 else
 120
 121 verilated_dram: litedram/generated/sim/litedram_core.v
 122         verilator $(VERILATOR_FLAGS) -CFLAGS $(VERILATOR_CFLAGS) -Wno-fatal --cc $<
 123         make -C obj_dir -f ../litedram/extras/sim_dram_verilate.mk VERILATOR_ROOT=$(VERILATOR_ROOT)
 124
 125 SIM_DRAM_CFLAGS  = -I. -Iobj_dir -Ilitedram/generated/sim -I$(VERILATOR_ROOT)/include -I$(VERILATOR_ROOT)/include/vltstd
 126 SIM_DRAM_CFLAGS += -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVL_PRINTF=printf -faligned-new
 127 sim_litedram_c.o: litedram/extras/sim_litedram_c.cpp verilated_dram
 128         $(CC)  $(CPPFLAGS) $(SIM_DRAM_CFLAGS) $(CFLAGS) -c $< -o $@
 129
 130 soc_dram_files = $(core_files) $(soc_files) litedram/extras/litedram-wrapper-l2.vhdl litedram/generated/sim/litedram-initmem.vhdl
 131 soc_dram_sim_files = $(soc_sim_files) litedram/extras/sim_litedram.vhdl
 132 soc_dram_sim_obj_files = $(soc_sim_obj_files) sim_litedram_c.o
 133 dram_link_files=-Wl,obj_dir/Vlitedram_core__ALL.a -Wl,obj_dir/verilated.o -Wl,obj_dir/verilated_vcd_c.o -Wl,-lstdc++
 134 soc_dram_sim_link=$(patsubst %,-Wl$(comma)%,$(soc_dram_sim_obj_files)) $(dram_link_files)
 135
 136 $(soc_dram_tbs): %: $(soc_dram_files) $(soc_dram_sim_files) $(soc_dram_sim_obj_files) $(flash_model_files) $(unisim_lib) $(fmf_lib) %.vhdl
 137         $(GHDL) -c $(GHDLFLAGS) $(soc_dram_sim_link) $(soc_dram_files) $(soc_dram_sim_files) $(flash_model_files) $@.vhdl -e $@
 138 endif
 139
 140 # Hello world
 141 MEMORY_SIZE=8192
 142 RAM_INIT_FILE=hello_world/hello_world.hex
 143
 144 # Micropython
 145 #MEMORY_SIZE=393216
 146 #RAM_INIT_FILE=micropython/firmware.hex
 147
 148 FPGA_TARGET ?= ORANGE-CRAB
 149
 150 # OrangeCrab with ECP85
 151 ifeq ($(FPGA_TARGET), ORANGE-CRAB)
 152 RESET_LOW=true
 153 CLK_INPUT=50000000
 154 CLK_FREQUENCY=40000000
 155 LPF=constraints/orange-crab.lpf
 156 PACKAGE=CSFBGA285
 157 NEXTPNR_FLAGS=--um5g-85k --freq 40
 158 OPENOCD_JTAG_CONFIG=openocd/olimex-arm-usb-tiny-h.cfg
 159 OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
 160 endif
 161
 162 # ECP5-EVN
 163 ifeq ($(FPGA_TARGET), ECP5-EVN)
 164 RESET_LOW=true
 165 CLK_INPUT=12000000
 166 CLK_FREQUENCY=40000000
 167 LPF=constraints/ecp5-evn.lpf
 168 PACKAGE=CABGA381
 169 NEXTPNR_FLAGS=--um5g-85k --freq 40
 170 OPENOCD_JTAG_CONFIG=openocd/ecp5-evn.cfg
 171 OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
 172 endif
 173
 174 # Arctic Tern with ECP85
 175 ifeq ($(FPGA_TARGET), ARCTIC-TERN)
 176 RESET_LOW=true
 177 CLK_INPUT=125000000
 178 CLK_FREQUENCY=48000000
 179 LPF=constraints/arctic-tern.lpf
 180 PACKAGE=CABGA381
 181 NEXTPNR_FLAGS=--um5g-85k --freq 48 --ignore-loops
 182 OPENOCD_JTAG_CONFIG=openocd/olimex-arm-usb-tiny-h.cfg
 183 OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
 184 toplevel=fpga/top-rcs-arctic-tern-bmc-card.vhdl
 185 soc_files   += litedram/extras/litedram-wrapper-l2.vhdl \
 186         litedram/generated/rcs-arctic-tern-bmc-card/litedram-initmem.vhdl
 187 soc_extra_v += litedram/generated/rcs-arctic-tern-bmc-card/litedram_core.v
 188 soc_extra_v += liteeth/generated/rcs-arctic-tern-bmc-card/liteeth_core.v
 189 soc_extra_v += pinyon/wishbone_interface.v
 190 soc_extra_v += tercel/phy.v
 191 soc_extra_v += tercel/wishbone_spi_master.v
 192 soc_extra_v += aquila/io_blocks.v
 193 soc_extra_v += aquila/lpc_slave.v
 194 soc_extra_v += aquila/wishbone_lpc_slave_interface.v
 195 soc_extra_v += aquila/third_party/async_fifo/async_bidir_fifo.v
 196 soc_extra_v += aquila/third_party/async_fifo/async_bidir_ramif_fifo.v
 197 soc_extra_v += aquila/third_party/async_fifo/async_fifo.v
 198 soc_extra_v += aquila/third_party/async_fifo/fifo_2mem.v
 199 soc_extra_v += aquila/third_party/async_fifo/fifomem_dp.v
 200 soc_extra_v += aquila/third_party/async_fifo/rptr_empty.v
 201 soc_extra_v += aquila/third_party/async_fifo/sync_ptr.v
 202 soc_extra_v += aquila/third_party/async_fifo/sync_r2w.v
 203 soc_extra_v += aquila/third_party/async_fifo/sync_w2r.v
 204 soc_extra_v += aquila/third_party/async_fifo/wptr_full.v
 205 endif
 206
 207 GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \
 208         -gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY)
 209
 210 clkgen=fpga/clk_gen_ecp5.vhd
 211 toplevel ?= fpga/top-generic.vhdl
 212 dmi_dtm=dmi_dtm_dummy.vhdl
 213
 214 ifeq ($(FPGA_TARGET), verilator)
 215 RESET_LOW=true
 216 CLK_INPUT=50000000
 217 CLK_FREQUENCY=50000000
 218 clkgen=fpga/clk_gen_bypass.vhd
 219 endif
 220
 221 fpga_files = fpga/soc_reset.vhdl \
 222         fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd fpga/main_bram.vhdl \
 223         nonrandom.vhdl
 224
 225 synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
 226
 227 microwatt.json: $(synth_files) $(RAM_INIT_FILE)
 228         $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; read_verilog $(uart_files) $(soc_extra_v); synth_ecp5 -json $@  $(SYNTH_ECP5_FLAGS)" $(uart_files)
 229
 230 microwatt.v: $(synth_files) $(RAM_INIT_FILE)
 231         $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; write_verilog $@"
 232
 233 # Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall
 234 microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c
 235         verilator $(VERILATOR_FLAGS) -CFLAGS "$(VERILATOR_CFLAGS) -DCLK_FREQUENCY=$(CLK_FREQUENCY)" --assert --cc $< --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c -o $@ -Iuart16550 -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT
 236         make -C obj_dir -f Vmicrowatt.mk
 237         @cp -f obj_dir/microwatt-verilator microwatt-verilator
 238
 239 microwatt_out.config: microwatt.json $(LPF)
 240         $(NEXTPNR) --json $< --lpf $(LPF) --textcfg $@.tmp $(NEXTPNR_FLAGS) --package $(PACKAGE)
 241         mv -f $@.tmp $@
 242
 243 microwatt.bit: microwatt_out.config
 244         $(ECPPACK) --svf microwatt.svf $< $@
 245
 246 microwatt.svf: microwatt.bit
 247
 248 prog: microwatt.svf
 249         $(OPENOCD) -f $(OPENOCD_JTAG_CONFIG) -f $(OPENOCD_DEVICE_CONFIG) -c "transport select jtag; init; svf $<; exit"
 250
 251 tests = $(sort $(patsubst tests/%.out,%,$(wildcard tests/*.out)))
 252 tests_console = $(sort $(patsubst tests/%.console_out,%,$(wildcard tests/*.console_out)))
 253
 254 tests_console: $(tests_console)
 255
 256 check: $(tests) tests_console test_micropython test_micropython_long tests_unit
 257
 258 check_light: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 test_micropython test_micropython_long tests_console tests_unit
 259
 260 $(tests): core_tb
 261         @./scripts/run_test.sh $@
 262
 263 $(tests_console): core_tb
 264         @./scripts/run_test_console.sh $@
 265
 266 test_micropython: core_tb
 267         @./scripts/test_micropython.py
 268
 269 test_micropython_long: core_tb
 270         @./scripts/test_micropython_long.py
 271
 272 tests_core_tb = $(patsubst %_tb,%_tb_test,$(core_tbs))
 273 tests_soc_tb = $(patsubst %_tb,%_tb_test,$(soc_tbs))
 274
 275 %_test: %
 276         ./$< --assert-level=error > /dev/null
 277
 278 tests_core: $(tests_core_tb)
 279
 280 tests_soc: $(tests_soc_tb)
 281
 282 # FIXME SOC tests have bit rotted, so disable for now
 283 #tests_unit: tests_core tests_soc
 284 tests_unit: tests_core
 285
 286 TAGS:
 287         find . -name '*.vhdl' | xargs ./scripts/vhdltags
 288
 289 .PHONY: TAGS
 290
 291 _clean:
 292         rm -f *.o *.cf $(all)
 293         rm -f fpga/*.o fpga/*.cf
 294         rm -f sim-unisim/*.o sim-unisim/*.cf
 295         rm -f litedram/extras/*.o
 296         rm -f TAGS
 297         rm -f scripts/mw_debug/*.o
 298         rm -f scripts/mw_debug/mw_debug
 299         rm -f microwatt.bin microwatt.json microwatt.svf microwatt_out.config
 300         rm -f microwatt.v microwatt-verilator
 301         rm -rf obj_dir/
 302
 303 clean: _clean
 304         make -f scripts/mw_debug/Makefile clean
 305         make -f hello_world/Makefile clean
 306
 307 distclean: _clean
 308         rm -f *~ fpga/*~ lib/*~ console/*~ include/*~
 309         rm -rf litedram/build
 310         rm -f litedram/extras/*~
 311         rm -f litedram/gen-src/*~
 312         rm -f litedram/gen-src/sdram_init/*~
 313         make -f scripts/mw_debug/Makefile distclean
 314         make -f hello_world/Makefile distclean
 315
 316 .PHONY: all prog check check_light clean distclean
 317 .PRECIOUS: microwatt.json microwatt_out.config microwatt.bit