cache_ram.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use ieee.math_real.all;
   5
   6 entity cache_ram is
   7     generic(
   8         ROW_BITS : integer := 16;
   9         WIDTH    : integer := 64;
  10         TRACE    : boolean := false;
  11         ADD_BUF  : boolean := false
  12         );
  13
  14     port(
  15         clk     : in  std_logic;
  16         rd_en   : in  std_logic;
  17         rd_addr : in  std_logic_vector(ROW_BITS - 1 downto 0);
  18         rd_data : out std_logic_vector(WIDTH - 1 downto 0);
  19         wr_sel  : in  std_logic_vector(WIDTH/8 - 1 downto 0);
  20         wr_addr : in  std_logic_vector(ROW_BITS - 1 downto 0);
  21         wr_data : in  std_logic_vector(WIDTH - 1 downto 0)
  22         );
  23
  24 end cache_ram;
  25
  26 architecture rtl of cache_ram is
  27     constant SIZE : integer := 2**ROW_BITS;
  28
  29     type ram_type is array (0 to SIZE - 1) of std_logic_vector(WIDTH - 1 downto 0);
  30     signal ram : ram_type;
  31     attribute ram_style : string;
  32     attribute ram_style of ram : signal is "block";
  33
  34     signal rd_data0 : std_logic_vector(WIDTH - 1 downto 0);
  35
  36 begin
  37     process(clk)
  38         variable lbit : integer range 0 to WIDTH - 1;
  39         variable mbit : integer range 0 to WIDTH - 1;
  40         variable widx : integer range 0 to SIZE - 1;
  41         constant sel0 : std_logic_vector(WIDTH/8 - 1 downto 0)
  42             := (others => '0');
  43     begin
  44         if rising_edge(clk) then
  45             if TRACE then
  46                 if wr_sel /= sel0 then
  47                     report "write a:" & to_hstring(wr_addr) &
  48                         " sel:" & to_hstring(wr_sel) &
  49                         " dat:" & to_hstring(wr_data);
  50                 end if;
  51             end if;
  52             for i in 0 to WIDTH/8-1 loop
  53                 lbit := i * 8;
  54                 mbit := lbit + 7;
  55                 widx := to_integer(unsigned(wr_addr));
  56                 if wr_sel(i) = '1' then
  57                     ram(widx)(mbit downto lbit) <= wr_data(mbit downto lbit);
  58                 end if;
  59             end loop;
  60             if rd_en = '1' then
  61                 rd_data0 <= ram(to_integer(unsigned(rd_addr)));
  62                 if TRACE then
  63                     report "read a:" & to_hstring(rd_addr) &
  64                         " dat:" & to_hstring(ram(to_integer(unsigned(rd_addr))));
  65                 end if;
  66             end if;
  67         end if;
  68     end process;
  69
  70     buf: if ADD_BUF generate
  71     begin
  72         process(clk)
  73         begin
  74             if rising_edge(clk) then
  75                 rd_data <= rd_data0;
  76             end if;
  77         end process;
  78     end generate;
  79
  80     nobuf: if not ADD_BUF generate
  81     begin
  82         rd_data <= rd_data0;
  83     end generate;
  84
  85 end;