core_flash_tb.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8
   9 entity core_flash_tb is
  10 end core_flash_tb;
  11
  12 architecture behave of core_flash_tb is
  13         signal clk, rst: std_logic;
  14
  15         -- testbench signals
  16         constant clk_period : time := 10 ns;
  17
  18         -- SPI
  19         signal spi_sck     : std_ulogic;
  20         signal spi_cs_n    : std_ulogic := '1';
  21         signal spi_sdat_o  : std_ulogic_vector(3 downto 0);
  22         signal spi_sdat_oe : std_ulogic_vector(3 downto 0);
  23         signal spi_sdat_i  : std_ulogic_vector(3 downto 0);
  24         signal fl_hold_n   : std_logic;
  25         signal fl_wp_n     : std_logic;
  26         signal fl_mosi     : std_logic;
  27         signal fl_miso     : std_logic;
  28 begin
  29
  30     soc0: entity work.soc
  31         generic map(
  32             SIM => true,
  33             MEMORY_SIZE => (384*1024),
  34             RAM_INIT_FILE => "main_ram.bin",
  35             CLK_FREQ => 100000000,
  36             HAS_SPI_FLASH    => true,
  37             SPI_FLASH_DLINES => 4,
  38             SPI_FLASH_OFFSET => 0
  39             )
  40         port map(
  41             rst => rst,
  42             system_clk => clk,
  43             spi_flash_sck     => spi_sck,
  44             spi_flash_cs_n    => spi_cs_n,
  45             spi_flash_sdat_o  => spi_sdat_o,
  46             spi_flash_sdat_oe => spi_sdat_oe,
  47             spi_flash_sdat_i  => spi_sdat_i
  48             );
  49
  50     flash: entity work.s25fl128s
  51         generic map (
  52             TimingModel => "S25FL128SAGNFI000_R_30pF",
  53             LongTimming => false,
  54             tdevice_PU => 10 ns,
  55             tdevice_PP256 => 100 ns,
  56             tdevice_PP512 => 100 ns,
  57             tdevice_WRR   => 100 ns
  58             )
  59         port map(
  60             SCK => spi_sck,
  61             SI => fl_mosi,
  62             CSNeg => spi_cs_n,
  63             HOLDNeg => fl_hold_n,
  64             WPNeg => fl_wp_n,
  65             RSTNeg => '1',
  66             SO => fl_miso
  67             );
  68
  69     fl_mosi   <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z';
  70     fl_miso   <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z';
  71     fl_wp_n   <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z';
  72     fl_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else '1' when spi_sdat_oe(0) = '1' else 'Z';
  73
  74     spi_sdat_i(0) <= fl_mosi;
  75     spi_sdat_i(1) <= fl_miso;
  76     spi_sdat_i(2) <= fl_wp_n;
  77     spi_sdat_i(3) <= fl_hold_n;
  78
  79     clk_process: process
  80     begin
  81         clk <= '0';
  82         wait for clk_period/2;
  83         clk <= '1';
  84         wait for clk_period/2;
  85     end process;
  86
  87     rst_process: process
  88     begin
  89         rst <= '1';
  90         wait for 10*clk_period;
  91         rst <= '0';
  92         wait;
  93     end process;
  94
  95     jtag: entity work.sim_jtag;
  96
  97 end;