Add Tercel PHY reset synchronization
[microwatt.git] / countzero_tb.vhdl
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4
5 library work;
6 use work.common.all;
7 use work.glibc_random.all;
8
9 entity countzero_tb is
10 end countzero_tb;
11
12 architecture behave of countzero_tb is
13 constant clk_period: time := 10 ns;
14 signal rs: std_ulogic_vector(63 downto 0);
15 signal is_32bit, count_right: std_ulogic := '0';
16 signal result: std_ulogic_vector(63 downto 0);
17 signal randno: std_ulogic_vector(63 downto 0);
18 signal clk: std_ulogic;
19
20 begin
21 zerocounter_0: entity work.zero_counter
22 port map (
23 clk => clk,
24 rs => rs,
25 result => result,
26 count_right => count_right,
27 is_32bit => is_32bit
28 );
29
30 clk_process: process
31 begin
32 clk <= '0';
33 wait for clk_period/2;
34 clk <= '1';
35 wait for clk_period/2;
36 end process;
37
38 stim_process: process
39 variable r: std_ulogic_vector(63 downto 0);
40 begin
41 -- test with input = 0
42 report "test zero input";
43 rs <= (others => '0');
44 is_32bit <= '0';
45 count_right <= '0';
46 wait for clk_period;
47 assert result = x"0000000000000040"
48 report "bad cntlzd 0 = " & to_hstring(result);
49 count_right <= '1';
50 wait for clk_period;
51 assert result = x"0000000000000040"
52 report "bad cnttzd 0 = " & to_hstring(result);
53 is_32bit <= '1';
54 count_right <= '0';
55 wait for clk_period;
56 assert result = x"0000000000000020"
57 report "bad cntlzw 0 = " & to_hstring(result);
58 count_right <= '1';
59 wait for clk_period;
60 assert result = x"0000000000000020"
61 report "bad cnttzw 0 = " & to_hstring(result);
62
63 report "test cntlzd/w";
64 count_right <= '0';
65 for j in 0 to 100 loop
66 r := pseudorand(64);
67 r(63) := '1';
68 for i in 0 to 63 loop
69 rs <= r;
70 is_32bit <= '0';
71 wait for clk_period;
72 assert to_integer(unsigned(result)) = i
73 report "bad cntlzd " & to_hstring(rs) & " -> " & to_hstring(result);
74 rs <= r(31 downto 0) & r(63 downto 32);
75 is_32bit <= '1';
76 wait for clk_period;
77 if i < 32 then
78 assert to_integer(unsigned(result)) = i
79 report "bad cntlzw " & to_hstring(rs) & " -> " & to_hstring(result);
80 else
81 assert to_integer(unsigned(result)) = 32
82 report "bad cntlzw " & to_hstring(rs) & " -> " & to_hstring(result);
83 end if;
84 r := '0' & r(63 downto 1);
85 end loop;
86 end loop;
87
88 report "test cnttzd/w";
89 count_right <= '1';
90 for j in 0 to 100 loop
91 r := pseudorand(64);
92 r(0) := '1';
93 for i in 0 to 63 loop
94 rs <= r;
95 is_32bit <= '0';
96 wait for clk_period;
97 assert to_integer(unsigned(result)) = i
98 report "bad cnttzd " & to_hstring(rs) & " -> " & to_hstring(result);
99 is_32bit <= '1';
100 wait for clk_period;
101 if i < 32 then
102 assert to_integer(unsigned(result)) = i
103 report "bad cnttzw " & to_hstring(rs) & " -> " & to_hstring(result);
104 else
105 assert to_integer(unsigned(result)) = 32
106 report "bad cnttzw " & to_hstring(rs) & " -> " & to_hstring(result);
107 end if;
108 r := r(62 downto 0) & '0';
109 end loop;
110 end loop;
111
112 std.env.finish;
113 end process;
114 end behave;