cr_file.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7
   8 entity cr_file is
   9     generic (
  10         SIM : boolean := false;
  11         -- Non-zero to enable log data collection
  12         LOG_LENGTH : natural := 0
  13         );
  14     port(
  15         clk   : in std_logic;
  16
  17         d_in  : in Decode2ToCrFileType;
  18         d_out : out CrFileToDecode2Type;
  19
  20         w_in  : in WritebackToCrFileType;
  21
  22         -- debug
  23         sim_dump : in std_ulogic;
  24
  25         log_out : out std_ulogic_vector(12 downto 0)
  26         );
  27 end entity cr_file;
  28
  29 architecture behaviour of cr_file is
  30     signal crs : std_ulogic_vector(31 downto 0) := (others => '0');
  31     signal crs_updated : std_ulogic_vector(31 downto 0);
  32     signal xerc : xer_common_t := xerc_init;
  33     signal xerc_updated : xer_common_t;
  34 begin
  35     cr_create_0: process(all)
  36         variable hi, lo : integer := 0;
  37         variable cr_tmp : std_ulogic_vector(31 downto 0) := (others => '0');
  38     begin
  39         cr_tmp := crs;
  40
  41         for i in 0 to 7 loop
  42             if w_in.write_cr_mask(i) = '1' then
  43                 lo := i*4;
  44                 hi := lo + 3;
  45                 cr_tmp(hi downto lo) := w_in.write_cr_data(hi downto lo);
  46             end if;
  47         end loop;
  48
  49         crs_updated <= cr_tmp;
  50
  51         if w_in.write_xerc_enable = '1' then
  52             xerc_updated <= w_in.write_xerc_data;
  53         else
  54             xerc_updated <= xerc;
  55         end if;
  56
  57     end process;
  58
  59     -- synchronous writes
  60     cr_write_0: process(clk)
  61     begin
  62         if rising_edge(clk) then
  63             if w_in.write_cr_enable = '1' then
  64                 report "Writing " & to_hstring(w_in.write_cr_data) & " to CR mask " & to_hstring(w_in.write_cr_mask);
  65                 crs <= crs_updated;
  66             end if;
  67             if w_in.write_xerc_enable = '1' then
  68                 report "Writing XERC";
  69                 xerc <= xerc_updated;
  70             end if;
  71         end if;
  72     end process;
  73
  74     -- asynchronous reads
  75     cr_read_0: process(all)
  76     begin
  77         -- just return the entire CR to make mfcrf easier for now
  78         if d_in.read = '1' then
  79             report "Reading CR " & to_hstring(crs_updated);
  80         end if;
  81         d_out.read_cr_data <= crs_updated;
  82         d_out.read_xerc_data <= xerc_updated;
  83     end process;
  84
  85     sim_dump_test: if SIM generate
  86         dump_cr: process(all)
  87         begin
  88             if sim_dump = '1' then
  89                 report "CR 00000000" & to_hstring(crs);
  90                 assert false report "end of test" severity failure;
  91             end if;
  92         end process;
  93     end generate;
  94
  95     cf_log: if LOG_LENGTH > 0 generate
  96         signal log_data : std_ulogic_vector(12 downto 0);
  97     begin
  98         cr_log: process(clk)
  99         begin
 100             if rising_edge(clk) then
 101                 log_data <= w_in.write_cr_enable &
 102                             w_in.write_cr_data(31 downto 28) &
 103                             w_in.write_cr_mask;
 104             end if;
 105         end process;
 106         log_out <= log_data;
 107     end generate;
 108
 109 end architecture behaviour;