dcache_tb.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3
   4 library work;
   5 use work.common.all;
   6 use work.wishbone_types.all;
   7
   8 entity dcache_tb is
   9 end dcache_tb;
  10
  11 architecture behave of dcache_tb is
  12     signal clk          : std_ulogic;
  13     signal rst          : std_ulogic;
  14
  15     signal d_in         : Loadstore1ToDcacheType;
  16     signal d_out        : DcacheToLoadstore1Type;
  17
  18     signal m_in         : MmuToDcacheType;
  19     signal m_out        : DcacheToMmuType;
  20
  21     signal wb_bram_in   : wishbone_master_out;
  22     signal wb_bram_out  : wishbone_slave_out;
  23
  24     constant clk_period : time := 10 ns;
  25 begin
  26     dcache0: entity work.dcache
  27         generic map(
  28             LINE_SIZE => 64,
  29             NUM_LINES => 4
  30             )
  31         port map(
  32             clk => clk,
  33             rst => rst,
  34             d_in => d_in,
  35             d_out => d_out,
  36             m_in => m_in,
  37             m_out => m_out,
  38             wishbone_out => wb_bram_in,
  39             wishbone_in => wb_bram_out
  40             );
  41
  42     -- BRAM Memory slave
  43     bram0: entity work.wishbone_bram_wrapper
  44         generic map(
  45             MEMORY_SIZE   => 1024,
  46             RAM_INIT_FILE => "icache_test.bin"
  47             )
  48         port map(
  49             clk => clk,
  50             rst => rst,
  51             wishbone_in => wb_bram_in,
  52             wishbone_out => wb_bram_out
  53             );
  54
  55     clk_process: process
  56     begin
  57         clk <= '0';
  58         wait for clk_period/2;
  59         clk <= '1';
  60         wait for clk_period/2;
  61     end process;
  62
  63     rst_process: process
  64     begin
  65         rst <= '1';
  66         wait for 2*clk_period;
  67         rst <= '0';
  68         wait;
  69     end process;
  70
  71     stim: process
  72     begin
  73         -- Clear stuff
  74         d_in.valid <= '0';
  75         d_in.load <= '0';
  76         d_in.nc <= '0';
  77         d_in.addr <= (others => '0');
  78         d_in.data <= (others => '0');
  79         m_in.valid <= '0';
  80         m_in.addr <= (others => '0');
  81         m_in.pte <= (others => '0');
  82
  83         wait for 4*clk_period;
  84         wait until rising_edge(clk);
  85
  86         -- Cacheable read of address 4
  87         d_in.load <= '1';
  88         d_in.nc <= '0';
  89         d_in.addr <= x"0000000000000004";
  90         d_in.valid <= '1';
  91         wait until rising_edge(clk);
  92         d_in.valid <= '0';
  93
  94         wait until rising_edge(clk) and d_out.valid = '1';
  95         assert d_out.data = x"0000000100000000"
  96             report "data @" & to_hstring(d_in.addr) &
  97             "=" & to_hstring(d_out.data) &
  98             " expected 0000000100000000"
  99             severity failure;
 100 --      wait for clk_period;
 101
 102         -- Cacheable read of address 30
 103         d_in.load <= '1';
 104         d_in.nc <= '0';
 105         d_in.addr <= x"0000000000000030";
 106         d_in.valid <= '1';
 107         wait until rising_edge(clk);
 108         d_in.valid <= '0';
 109
 110         wait until rising_edge(clk) and d_out.valid = '1';
 111         assert d_out.data = x"0000000D0000000C"
 112             report "data @" & to_hstring(d_in.addr) &
 113             "=" & to_hstring(d_out.data) &
 114             " expected 0000000D0000000C"
 115             severity failure;
 116
 117         -- Non-cacheable read of address 100
 118         d_in.load <= '1';
 119         d_in.nc <= '1';
 120         d_in.addr <= x"0000000000000100";
 121         d_in.valid <= '1';
 122         wait until rising_edge(clk);
 123         d_in.valid <= '0';
 124         wait until rising_edge(clk) and d_out.valid = '1';
 125         assert d_out.data = x"0000004100000040"
 126             report "data @" & to_hstring(d_in.addr) &
 127             "=" & to_hstring(d_out.data) &
 128             " expected 0000004100000040"
 129             severity failure;
 130
 131         wait until rising_edge(clk);
 132         wait until rising_edge(clk);
 133         wait until rising_edge(clk);
 134         wait until rising_edge(clk);
 135
 136         std.env.finish;
 137     end process;
 138 end;