Add Tercel PHY reset synchronization
[microwatt.git] / decode_types.vhdl
1 library ieee;
2 use ieee.std_logic_1164.all;
3
4 package decode_types is
5 type insn_type_t is (OP_ILLEGAL, OP_NOP, OP_ADD,
6 OP_AND, OP_ATTN, OP_B, OP_BC, OP_BCREG,
7 OP_BPERM, OP_CMP, OP_CMPB, OP_CMPEQB, OP_CMPRB,
8 OP_CNTZ, OP_CROP,
9 OP_DARN, OP_DCBF, OP_DCBST, OP_DCBT, OP_DCBTST,
10 OP_DCBZ, OP_DIV, OP_DIVE, OP_EXTS, OP_EXTSWSLI,
11 OP_FPOP, OP_FPOP_I,
12 OP_ICBI, OP_ICBT, OP_ISEL, OP_ISYNC,
13 OP_LOAD, OP_STORE,
14 OP_MCRXRX, OP_MFCR, OP_MFMSR, OP_MFSPR, OP_MOD,
15 OP_MTCRF, OP_MTMSRD, OP_MTSPR, OP_MUL_L64,
16 OP_MUL_H64, OP_MUL_H32, OP_OR,
17 OP_POPCNT, OP_PRTY, OP_RFID,
18 OP_RLC, OP_RLCL, OP_RLCR, OP_SC, OP_SETB,
19 OP_SHL, OP_SHR,
20 OP_SYNC, OP_TLBIE, OP_TRAP,
21 OP_XOR,
22 OP_BCD, OP_ADDG6S,
23 OP_FETCH_FAILED
24 );
25 type input_reg_a_t is (NONE, RA, RA_OR_ZERO, SPR, CIA, FRA);
26 type input_reg_b_t is (NONE, RB, CONST_UI, CONST_SI, CONST_SI_HI, CONST_UI_HI, CONST_LI, CONST_BD,
27 CONST_DXHI4, CONST_DS, CONST_DQ, CONST_M1, CONST_SH, CONST_SH32, SPR, FRB);
28 type input_reg_c_t is (NONE, RS, RCR, FRC, FRS);
29 type output_reg_a_t is (NONE, RT, RA, SPR, FRT);
30 type rc_t is (NONE, ONE, RC);
31 type carry_in_t is (ZERO, CA, OV, ONE);
32
33 constant SH_OFFSET : integer := 0;
34 constant MB_OFFSET : integer := 1;
35 constant ME_OFFSET : integer := 1;
36 constant SH32_OFFSET : integer := 0;
37 constant MB32_OFFSET : integer := 1;
38 constant ME32_OFFSET : integer := 2;
39
40 constant FXM_OFFSET : integer := 0;
41
42 constant BO_OFFSET : integer := 0;
43 constant BI_OFFSET : integer := 1;
44 constant BH_OFFSET : integer := 2;
45
46 constant BF_OFFSET : integer := 0;
47 constant L_OFFSET : integer := 1;
48
49 constant TOO_OFFSET : integer := 0;
50
51 type unit_t is (NONE, ALU, LDST, FPU);
52 type facility_t is (NONE, FPU);
53 type length_t is (NONE, is1B, is2B, is4B, is8B);
54
55 type repeat_t is (NONE, -- instruction is not repeated
56 DRSE, -- double RS, endian twist
57 DRTE, -- double RT, endian twist
58 DUPD); -- update-form load
59
60 type decode_rom_t is record
61 unit : unit_t;
62 facility : facility_t;
63 insn_type : insn_type_t;
64 input_reg_a : input_reg_a_t;
65 input_reg_b : input_reg_b_t;
66 input_reg_c : input_reg_c_t;
67 output_reg_a : output_reg_a_t;
68
69 input_cr : std_ulogic;
70 output_cr : std_ulogic;
71
72 invert_a : std_ulogic;
73 invert_out : std_ulogic;
74 input_carry : carry_in_t;
75 output_carry : std_ulogic;
76
77 -- load/store signals
78 length : length_t;
79 byte_reverse : std_ulogic;
80 sign_extend : std_ulogic;
81 update : std_ulogic;
82 reserve : std_ulogic;
83
84 -- multiplier and ALU signals
85 is_32bit : std_ulogic;
86 is_signed : std_ulogic;
87
88 rc : rc_t;
89 lr : std_ulogic;
90
91 sgl_pipe : std_ulogic;
92 repeat : repeat_t;
93 end record;
94 constant decode_rom_init : decode_rom_t := (unit => NONE, facility => NONE,
95 insn_type => OP_ILLEGAL, input_reg_a => NONE,
96 input_reg_b => NONE, input_reg_c => NONE,
97 output_reg_a => NONE, input_cr => '0', output_cr => '0',
98 invert_a => '0', invert_out => '0', input_carry => ZERO, output_carry => '0',
99 length => NONE, byte_reverse => '0', sign_extend => '0',
100 update => '0', reserve => '0', is_32bit => '0',
101 is_signed => '0', rc => NONE, lr => '0', sgl_pipe => '0', repeat => NONE);
102
103 end decode_types;
104
105 package body decode_types is
106 end decode_types;