dmi_dtm_dummy.vhdl

   1 -- Dummy/empty DMI interface to make toplevel happy on unsupported FPGAs
   2
   3 library ieee;
   4 use ieee.std_logic_1164.all;
   5
   6 library work;
   7 use work.wishbone_types.all;
   8
   9 entity dmi_dtm is
  10     generic(ABITS : INTEGER:=8;
  11             DBITS : INTEGER:=32);
  12
  13     port(sys_clk        : in std_ulogic;
  14          sys_reset      : in std_ulogic;
  15          dmi_addr       : out std_ulogic_vector(ABITS - 1 downto 0);
  16          dmi_din        : in std_ulogic_vector(DBITS - 1 downto 0);
  17          dmi_dout       : out std_ulogic_vector(DBITS - 1 downto 0);
  18          dmi_req        : out std_ulogic;
  19          dmi_wr         : out std_ulogic;
  20          dmi_ack        : in std_ulogic
  21          );
  22 end entity dmi_dtm;
  23
  24 architecture behaviour of dmi_dtm is
  25 begin
  26     dmi_addr <= (others => '0');
  27     dmi_dout <= (others => '0');
  28     dmi_req  <= '0';
  29     dmi_wr   <= '0';
  30 end architecture behaviour;
  31